80ksw0001 Integrated Device Technology, 80ksw0001 Datasheet

80ksw0001

Manufacturer Part Number

80ksw0001

Description

Srio Pre-processing Switch Pps Gen 2 For Dsp Clusters

Manufacturer

Integrated Device Technology

Datasheet

1.80KSW0001.pdf (3 pages)

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Download datasheet (241Kb)

1 Device Overview

Switch (PPS) family of devices. The PPS is designed to be a central component

to DSP cluster architectures. It supports true serial RapidIO

(unicast, multicast, or broadcast) from any input to any output port. The PPS

accelerates baseband processing in support of a variety of wireless standards.

The 80KSW0001 can also optionally perform a variety of data processing on the

payload of sample packets to accelerate the subsequent algorithmic operations

of a receiving processor (DSP, CRP, FPGA). The special processing capabili-

ties may also be used for media gateways, video imaging such as that in medical

equipment or high-end surveillance, or similar signal processing-intensive appli-

cations.

2 Features

3 Block Diagram

The 80KSW0001 is a member of IDT’s serial RapidIO

–

Interfaces - sRIO

12 Serial RapidIO (sRIO) v 1.3 full duplex lanes

Lane Rates selectable; 3.125Gbps, 2.5Gbps, or 1.25Gbps

Short- or Long-haul reach for each lane at all rates

2 Configurations: a) 10 Ports (IDT70K2000 compatible) b) 12 ports

(compatibility possible with new configuration software)

sRIO Multicast support (10 simultaneous masks)

Support for 4 sRIO priorities

Port Loopback Debug Feature

Software assisted error recovery, supporting hot swap

SERDES

Lane 0

Lane 1

Lane 2

Lane 3

Lane 0

Lane 1

Lane 2

Lane 3

sRIO

Serial RapidIO

Pre-Processing Switch

for DSP Clusters

Quad 0

Logical

Quad 1

Logical

sRIO

packet switching

Pre-Processing

Block

PPSc

PPSc 3

PPSc 2

PPSc 1

1 of 3

PPSc 0

Maintenance

Management

Buffer

Input

Error

File

Processor

Packet

–

– Each PPSc offers 24 Gbps peak input bandwidth, 24 Gbps

–

– FCBGA 324-ball grid array, 19mm x 19mm, 1.0mm ball pitch

Interfaces - I

Switch

4 Independent Packet Processing Scenarios (PPSc)

DMA Support

Packet Trace

FIR Filtering

Synchronization

Full JTAG Boundary Scan Support (IEEE1149.1 & 1149.6)

2 Package Options:

JTAG

Output

Buffer

One I

30 Gbps peak throughput (max throughput for all ports)

peak processing throughput, 10 Gbps peak unicast output, 24

Gbps peak multicast with decoded packets

Resultant output data may be segmented into up to 8 smaller output

data (SWRITE only)

Automatic 34-bit target memory address generation per sRIO packet

Each Port provides the ability to match the first 160 bits of any packet

against up to 4 programmable values as comparison criteria to copy

the packet to a programmable output trace port

Each PPSc supports the ability to perform 2.5 GMACs per second,

and an aggregate of 9.9 GMACs

Packet alignment and deskew capabilities in support of time-based

domains

FCBGA 676-ball grid array, 27 mm x 27mm, 1.0mm ball pitch

C port for configuration and error reporting

Quad 2

Logical

sRIO

SERDES

Lane 0

Lane 1

Lane 2

Lane 3

sRIO

Product Brief

December 17, 2007

80KSW0001

DSC 5697

Related parts for 80ksw0001

80ksw0001 Summary of contents

Page 1

... The PPS accelerates baseband processing in support of a variety of wireless standards. The 80KSW0001 can also optionally perform a variety of data processing on the payload of sample packets to accelerate the subsequent algorithmic operations of a receiving processor (DSP, CRP, FPGA). The special processing capabili- ...

Page 2

... Input packets packets with other destination IDs are switched as defined by the transport layer sRIO specification. The packet manipulation in the 80KSW0001 is transparent to the sRIO protocol. The 80KSW0001 receives the packets from unique ports. Depending on the device ID field within a received packet, two functions can be performed by the device: ...

Page 3

... By utilizing the GPPScs, a given data stream may have several types of processing performed and transferred to the same or multiple output ports. The 80KSW0001 can be programmed through a CPU or a DSP connected to one of the sRIO ports of the device or with a CPU connected JTAG bus. This option is added to allow the user to use a conventional CPU instead of a sRIO interface. ...

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