9db233 Integrated Device Technology, 9db233 Datasheet
9db233
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9db233 Summary of contents
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... General Description: The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking ...
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... Two Output Differential Buffer for PCIe Gen3 Pin Configuration Power Distribution Table Pin Number VDD GND 5,9,12,16 6, Analog VDD & GND for PLL core Two Output Differential Buffer for PCIe Gen3 ® IDT PLL_BW 1 20 VDDA SRC_IN 2 19 GNDA ...
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... Two Output Differential Buffer for PCIe Gen3 Pin Description PIN # PIN NAME PIN TYPE 3.3V input for selecting PLL Band Width 1 PLL_BW low, 1= high 2 SRC_IN IN 0.7 V Differential SRC TRUE input 3 SRC_IN# IN 0.7 V Differential SRC COMPLEMENTARY input Activ e low input for enabling DIF pair 0. This pin has an internal pull-down. ...
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... Two Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL 3.3V Core Supply Voltage VDDA 3.3V Logic Supply Voltage VDD Input Low Voltage V IL Input High Voltage V IH Input High Voltage V IHSMB Storage Temperature Ts Junction Temperature Tj Input ESD protection ...
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... Two Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Clock Input Parameters Supply Voltage VDD = 3.3 V +/-5% COM IND; PARAMETER SYMBOL Input High Voltage - DIF_IN V IHDIF Input Low Voltage - DIF_IN V ILDIF Input Common Mode V COM Voltage - DIF_IN Input Amplitude - DIF_IN ...
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... Two Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics Supply Voltage VDD = 3.3 V +/-5% COM IND; PARAMETER SYMBOL PLL Bandwidth BW PLL Jitter Peaking t JPEAK Duty Cycle t DC Duty Cycle Distortion t DCD ...
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... Two Output Differential Buffer for PCIe Gen3 Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max ...
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... Two Output Differential Buffer for PCIe Gen3 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm 0.45v 0.22v 1.08 0.58 0.28 0.6 0.80 0.40 0.6 0.60 0.3 1.2 R1a = R1b = R1 R2a = R2b = R2 Figure 3 L1' HCSL Output Buffer Component R5a, R5b R6a, R6b Cc Vcm Figure Two Output Differential Buffer for PCIe Gen3 ® ...
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... Two Output Differential Buffer for PCIe Gen3 General SMBus serial interface information for the ICS9DB233 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ...
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... Two Output Differential Buffer for PCIe Gen3 SMB us Table: Device C ontrol Register, READ/WRITE ADDRESS (D4/D5) Byte 0 Pin # - Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 Bit 1 - PLL BW #adjust - Bit 0 PLL Enable SMB us Table: Output Enable Register Byte 1 Pin # Bit 7 - Bit Bit 5 Bit 4 - Bit 3 ...
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... Two Output Differential Buffer for PCIe Gen3 SMBus Table: DEVICE ID Byte 4 Pin # Bit Bit 6 Bit Bit 4 - Bit 3 Bit Bit 1 - Bit 0 SMBus Table: Byte Count Register Byte 5 Pin # - Bit 7 Bit Bit 5 - Bit 4 Bit Bit 2 - Bit 1 Bit 0 - Two Output Differential Buffer for PCIe Gen3 ® ...
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... Two Output Differential Buffer for PCIe Gen3 20-pin SSOP Package Drawing and Dimensions Two Output Differential Buffer for PCIe Gen3 ® IDT 20-Lead, 150 mil SSOP (QSOP) In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 1.35 1.75 A1 0.10 0. 1.50 b 0.20 0.30 c 0.18 0.25 D SEE VARIATIONS E 5.80 6.20 E1 3.80 4.00 e 0.635 BASIC L 0 ...
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... Tape and Reel 9DB233AFILF Tubes 9DB233AFILFT Tape and Reel 9DB233AGLF Tubes 9DB233AGLFT Tape and Reel 9DB233AGILF Tubes 9DB233AGILFT Tape and Reel "LF" after the package code are the Pb-Free configuration and are RoHS compliant. "A" is the device revision designator (will not correlate to the datasheet revision). ...
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... Two Output Differential Buffer for PCIe Gen3 Revision History Rev. Who Issue Date Description 0.1 RDW 4/28/2010 1. Initial Release 1. Updated Pin names to match other 9DB devices CLKREQ# becomes OE# and PCIEXyy becomes DIF_yy 2. Updated maximum rise/fall time to 550ps from 700ps. This translates to a minimum slew rate of 0 ...