xrd9816acv Exar Corporation, xrd9816acv Datasheet
xrd9816acv
Available stocks
Related parts for xrd9816acv
xrd9816acv Summary of contents
Page 1
... AC/DC coupling, making the XRD9814/9816 suitable for use in CCD, CIS and other data acquisition applications. ORDERING INFORMATION Part No. XRD9814ACV XRD9816ACV Rev. 1.00 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 XRD9814/XRD9816 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors ...
Page 2
XRD9814/9816 INTERNAL TIMING CONTROL PROGRAMMABLE RED(+) BUFFERED CDS or S/H RED(-) AGND1 PROGRAMMABLE GRN(+) BUFFERED CDS or S/H GRN(-) AGND2 PROGRAMMABLE BLU(+) BUFFERED CDS or S/H BLU(-) Rev. 1.00 10-BIT PGA REGISTER 10-BIT DAC REGISTER 10-BIT 3-1 PGA MUX REGISTER ...
Page 3
PIN CONFIGURATION DB8 1 DB7 2 DB6 3 DB5 4 DB4 5 DB3 6 DB2 7 DB1 8 DB0 9 N/C 10 N/C 11 AVDD3 12 Note: Pins 17,20 and 23 should be connected to AGND2 to improve noise immunity ...
Page 4
XRD9814/9816 PIN DESCRIPTION - XRD9814 (CONT'D) Pin No. Name 16 RED(-) 17 N/C 18 GRN(+) 19 GRN(-) 20 N/C 21 BLU(+) 22 BLU(-) 23 N/C 24 TEST1 25 TEST2 26 CREF 27 CAPP 28 CAPN 29 SGND 30 AGND1 31 ...
Page 5
PIN CONFIGURATION DB10 1 DB9 2 DB8 3 DB7 4 DB6 5 DB5 6 DB4 7 DB3 8 DB2 9 DB1 10 DB0 11 AVDD3 12 Note: Pins 17,20 and 23 should be connected to AGND2 to improve noise immunity ...
Page 6
XRD9814/9816 Pin Configuration - XRD9816 Pin No. Name 16 RED(-) 17 N/C 18 GRN(+) 19 GRN(-) 20 N/C 21 BLU(+) 22 BLU(-) 23 N/C 24 TEST1 25 TEST2 26 CREF 27 CAPP 28 CAPN 29 SGND 30 AGND1 31 AV ...
Page 7
ELECTRICAL CHARACTERISTICS AV =DV =5.0V, ADCCLK=6MHz, Input Range = 2V, Ta= Parameter Symbol A/D CONVERTER Resolution Resolution Maximum Conversion Rate Differential Non-Linearity DNL Differential Non-Linearity DNL Monotonicity Monotonicity Input Referred Offset ZSE Offset Drift ZSD Input Referred Gain ...
Page 8
XRD9814/9816 ELECTRICAL CHARACTERISTICS (CONT’D) AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified Parameter Symbol OFFSET SPECIFICATIONS Fine Offset Adjustment Min OFR Fine Offset Adjustment Max OFR Fine Offset Adjustment Step OFRES Fine Offset Adjustment OFRL Linearity Gross Offset Adjustment Min OFGR Gross ...
Page 9
ELECTRICAL CHARACTERISTICS (CONT’D) AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified Parameter Symbol TIMING SPECIFICATIONS ADCCLK Pulse Width BSAMP falling edge delay from rising ADCCLK BSAMP falling edge to VSAMP falling edge. ADCCLK Period (1 Ch. Mode) ADCCLK Period (3 Ch. Mode) ...
Page 10
XRD9814/9816 ELECTRICAL CHARACTERISTICS (CONT’D) AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified Parameter Symbol DATA READBACK SPECIFICATIONS Address Access Time taa (1) Output Enable Access Time taoe (1) ADC DIGITAL OUTPUT SPECIFICATIONS Output Delay tod Tri-State to Data Valid tlz Output Enable ...
Page 11
Function A2 A1 Configuration Reg # Configuration Reg # Red Gain 0 1 Green Gain 0 1 Blue Gain 1 0 Red Offset 1 0 Green Offset 1 1 Blue Offset 1 1 Table 1. XRD9814/9816 ...
Page 12
XRD9814/9816 Bit Address Assignment PB9 Not Used PB8 Not Used PB7 Not Used PB6 Not Used PB5 Not Used PB4 PB3 CDS Clamp Voltage 01 AV (Black Level) PB2 Not Used PB1 Stand-By Mode ...
Page 13
Function Red Gain Green Gain Blue Gain Red Offset PB9-PB8 gross adj PB7-PB0 fine adj Green Offset PB9-PB8 gross adj PB7-PB0 fine ...
Page 14
XRD9814/9816 GENERAL DESCRIPTION The XRD9814/9816 contains all of the circuitry re- quired to create a complete 3-channel signal processor /digitizer for use in CCD/CIS imaging systems. Each channel includes a correlated double sampler (CDS), programmable gain amplifier (PGA) and channel ...
Page 15
No-Clamp Mode (S/H with DC input) Used for DC coupled inputs. AC coupled inputs must be externally clamped to the proper common-mode input voltage of the XRD9814/9816. Note: Pixel clamp is the default clamp mode. BSAMP LCLMP PB6 PB7 A/D ...
Page 16
XRD9814/9816 VSAMP Timing This allows the user to select one of two VSAMP timing controls. Timing Option #2 allows the rising edge of VSAMP to occur approximately one-half ADCCLK earlier than Option #1. This does not affect internal timing and ...
Page 17
Code PGA Gain = 1024 where Code represents the binary contents of the 10- bit gain setting register. Channel Offset Adjustment The gross offset correction for each channel is progammable from -400mV to +200mV. It ...
Page 18
XRD9814/9816 (Correlated Double Sampling) Correlated double sampling is a technique used to level shift and acquire CCD output signals whose informa- tion is equal to the difference between consecutive reference (black) and signal (video) samples. The CDS process consists of ...
Page 19
CIS/Sample and Hold Mode The XRD9814/9816 also supports operation for Con- tact Image Sensor (CIS) and S/H applications. The green channel is synchronized on the rising edge of the first ADCCLK after the falling edge of VSAMP. For DC ...
Page 20
XRD9814/9816 Maximum Capacitance (CDS Pixel Mode) Limitation #1 Since the black level is clamped during each pixel period the input bias current contributes an insignifi- cant amount of droop during one pixel period. However, pixel-pixel variations in the black level ...
Page 21
Minimum Capacitance (CDS Line Mode) In general, the minimum value coupling capacitance is limited by the amount of droop which can occur before the input voltage range of the input amplifier is ex- ceeded. The input capacitor droop is related ...
Page 22
XRD9814/9816 tap CCDIN ADCCLK BSAMP VSAMP tstl tpwv Clamp (Internal to XRD9814/XRD9816) Notes: (1) VSAMP Timing Option #1 uses tvrcf (tvrcr is not required) (2) VSAMP Timing Option #2 uses tvrcr (tvrcf is not required) VSAMP Timing Option #2 only ...
Page 23
CCDIN LCLMP ADCCLK BSAMP VSAMP tpwv tstl Clamp (Internal to XRD9814/XRD9816) Notes: (1) VSAMP Timing Option #1 uses tvrcf (tvrcr is not required) (2) VSAMP Timing Option #2 uses tvrcr (tvrcf is not required) VSAMP Timing Option #2 only ...
Page 24
XRD9814/9816 tap CCDIN ADCCLK tstl tvfcr BSAMP VSAMP tpwv Clamp (Internal to XRD9814/XRD9816) Figure 5. 1-Channel CDS Mode - Pixel Clamp Configuration Register #1: Pixel Clamp (PB7=0, PB6=0) Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11) Inverted Polarity (PB2=0) ...
Page 25
CCDIN LCLMP ADCCLK tstl tvfcr BSAMP VSAMP tpwv Clamp (Internal to XRD9814/XRD9816) Notes: (1) Only VSAMP timing option #1 is supported in 1-channel mode Figure 6. 1-Channel CDS Mode - Line Clamp Configuration Register #1: CDS Line Clamp (PB7=0, ...
Page 26
XRD9814/9816 tap CIS LCLMP ADCCLK VSAMP tstl tpwv Clamp (Internal to XRD9814/XRD9816) Figure 7. 3-Channel S/H Mode - Line Clamp (AC Coupled) Configuration Register #1: S/H Line Clamp (PB7=1, PB6=1) RGB (PB4=0, PB3=0) Non-Inverted Polarity (PB2=1) Input Buffer Enabled (PB1=1) ...
Page 27
CIS ADCCLK VSAMP tstl tpwv Clamp (Internal to XRD9814/XRD9816) Notes: (1) VSAMP Timing option #1 uses tvrcf (tvrcr is not required) (2) VSAMP Timing option #2 uses tvrcr (tvrcf is not required) Figure 8. 3-Channel S/H Mode - No ...
Page 28
XRD9814/9816 tap CIS LCLMP ADCCLK tstl VSAMP tpwv Clamp (Internal to XRD9814/XRD9816) Figure 9. 1-Channel S/H Mode - Line Clamp (AC Coupled) Configuration Register #1: S/H Line Clamp (PB7=1, PB6=1) Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11) Non-Inverted ...
Page 29
CIS ADCCLK VSAMP tpwv Clamp (Internal to XRD9814/XRD9816) Notes: (1) Only VSAMP timing option #1 is supported in 1-channel mode Figure 10. 1-Channel S/H Mode - No Clamp (DC Coupled) Configuration Register #1: S/H No Clamp (PB7=1, PB6=0) Single ...
Page 30
XRD9814/9816 5.0 V 4.7 V VCLAMP=4.2 V Reset Ground Typical Operation, VCLAMP = 4.2V, (PB4 = 0, PB3 = 0) VRESET = 0.5V, VVIDEO = 2.0V = FSR of XRD9814/9816 Figure 11. VCLAMP Setting Example 1 5.2 V 5.0 V ...
Page 31
Pixel (n) CCDOUT (Parallel RGB) ADCCLK BSAMP ADC Samples Green VSAMP Figure 13. 3-Channel CDS Pixel Clamp Synchronization and ADC Latency Timing Pixel (n) Pixel (n+1) Pixel (n+2) CCDOUT (Green Input) ADCCLK BSAMP VSAMP Figure 14. 1-Channel CDS Pixel Clamp ...
Page 32
XRD9814/9816 Pixel (n) CISOUT (Parallel RGB) ADCCLK ADC Samples Green VSAMP Figure 15. 3-Channel S/H Synchronization and ADC Latency Timing Pixel (n) Pixel (n+1) Pixel (n+2) CISOUT (Green Input) ADCCLK VSAMP Figure 16. 1-Channel S/H Synchronization and ADC Latency Timing ...
Page 33
SCLK (Pin 41) tds SDI PB9 (Pin 40) LOAD (Pin 39) SCLK/ DB12/DB14 (Pin 45) tds SDI/ DB13/DB15 (Pin 44) tlcs tlch LOAD (Pin 39) Figure 18. Write Timing (INSEL = 1) Rev. 1.00 ...
Page 34
XRD9814/9816 XRD9814/9816 Read Back Timing LOAD SCLK Enables Read-back SDI 001XXXXXXXXX1 Output Cfig2 (DBx) ADC Output Data Reg data Read-back Cfig2 data Write to Cfig2, bit0 to enable readback & Address Cfig2 for register read-back Figure 19. XRD9814/9816 Read-Back Timing ...
Page 35
OEB ADCCLK DB13:0/ TRI-STATE DB15:0 tlz LOAD Figure 20. ADC Digital Output Timing (OUTSEL = 0) OEB ADCCLK DB13:0/ TRI-STATE N-8 DB15:0 (LSB 6/8-BITS) tlz LOAD Figure 21. ADC Digital Output Timing (OUTSEL = 1) Rev. 1.00 XRD9814/9816 N+1 N ...
Page 36
XRD9814/9816 CCD tstl N-1 N VSAMP ADCCLK ADCOUT Non Valid Data Figure 22. XRD9814/XRD9816 Pipeline Latency ADCCLK/SYNCHRONIZATION EVENTS 1 Necessary / No Sampling Events Occur 2 Beginning of Synchronization / Samples Green (N-1) / Converts Unkown ...
Page 37
Application Notes Figure 23. Single Channel DC-Coupled Mode C 100pF 100pF S Figure 24. Single Channel AC-Coupled Mode Rev. 1.00 Avdd Dvdd ...
Page 38
XRD9814/9816 Figure 25. Triple Channel DC-Coupled Mode 100pF 100pF 100pF / C 100pF I S 100pF 100pF Figure 26. Triple Channel AC-Coupled Mode Rev. 1.00 Avdd Dvdd ...
Page 39
INSEL/OUTSEL Data Output Format There are two control signals for setting the output data format and the serial load control. INSEL is used to select the mode for programming the serial port. To use the external pins sdi, sclk and ...
Page 40
XRD9814/9816 XRD9814 / XRD9816 Figure 29. 8-Bit Nibble Output (OUTSEL=1), External Serial Load (INSEL=0) DB12/DB14/sclk XRD9814 / XRD9816 Figure 30. 8-Bit Nibble Output (OUTSEL=1), Bi-Directional Serial Load (INSEL=1) Rev. 1.00 8-Bit Nibble DB13/DB15 DB12/DB14 DB6/DB8 External Serial Load sdi sclk ...
Page 41
XRD9814 1 Channel CIS No Clamp, AVDD = DVDD = 5V 6MSPS, 2V Reference 1.5 1 0.5 0 -0.5 -1 -1.5 Graph 1. XRD9814 1-Channel CIS S/H No Clamp DNL Plot Rev. 1.00 XRD9814/9816 DNL PLOT Codes 41 ...
Page 42
XRD9814/9816 XRD9814 1-Channel CDS Pixel Clamp, AVDD = DVDD = 5V 6MSPS, 2V Reference, DNL Plot 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 Graph 2. XRD9814 1-Channel CDS Pixel Clamp DNL Plot Rev. 1.00 Codes 42 ...
Page 43
XRD9814 3-Channel CDS Pixel Clamp, AVDD = DVDD = 5V 6MSPS, 2V Reference, DNL Plot 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 Graph 3. XRD9814 3-Channel CDS Pixel Clamp DNL Plot Rev. 1.00 XRD9814/9816 Code 43 ...
Page 44
XRD9814/9816 XRD9814 1CH DC CIS Input Referred Noise vs. Gain of 1. V/V ADCCLK = 1MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V 3 2.5 2 1.5 1 0.5 0 1.63 Graph 4. XRD9814 ...
Page 45
XRD9814 1CH DC CIS Input Referred Noise vs. Gain of 1. V/V ADCCLK = 6MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V 4 3.5 3 2.5 2 1.5 1 0.5 0 1.63 Graph 5. ...
Page 46
XRD9814/9816 XRD9814 3CH CDS Input Referred Noise vs. Gain of 1. V/V ADCCLK = 6MSPS, AVDD = 5V, DVDD = 3V, ADC Input Range = 3Vpp 1.63 2.75 Graph 6. XRD9814 ...
Page 47
Graph 7. XRD9814/9816 Gain vs. Gain Code Rev. 1.00 XRD9814/9816 XRD9814/9816 Gain vs. Gain Code 383 447 511 575 639 703 767 Gain ...
Page 48
XRD9814/9816 XRD9814/9816 3CH CDS, AVDD = 5V, DVDD = 3V 6MSPS, 3Vpp, Gain = 0 V/V Inputs AC Coupled to Ground with 100pF Capacitors 100 0.50 0.78 1.06 ...
Page 49
XRD9816 3-Channel CDS Pixel Clamp Mode, AVDD = DVDD = 5V 6MSPS, 2V Reference, DNL Plot 1.5 1 0.5 0 -0.5 -1 Graph 9. XRD9816 3-Channel CDS Pixel Clamp DNL Plot Rev. 1.00 XRD9814/9816 Codes 49 ...
Page 50
XRD9814/9816 XRD9816 1CH DC CIS Input Referred Noise vs. Gain of 1. V/V ADCCLK = 1MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 1.63 Graph 10. XRD9816 ...
Page 51
XRD9816 1CH DC CIS Input Referred Noise vs. Gain of 1. V/V ADCCLK = 6MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 1.63 Graph 11. XRD9816 ...
Page 52
XRD9814/9816 Rev. 1.00 52 ...
Page 53
... EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...