uss820d-db ETC-unknow, uss820d-db Datasheet
uss820d-db
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uss820d-db Summary of contents
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USS-820D USB Device Controller Features Full compliance with the Universal Serial Bus I Specification Revision 1.1. Backward compatible with USS-820B and I USS-820C revisions. Self-powered or bus-powered USB device. Meets I USB power specifications for bus-powered devices. Full-speed USB device ...
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USB Device Controller Contents Features ....................................................................................................................................................................1 New Features After Revision B .................................................................................................................................1 Applications ...............................................................................................................................................................1 Description.................................................................................................................................................................3 Serial Interface Engine............................................................................................................................................ 3 Protocol Layer ......................................................................................................................................................... 4 FIFO Control ........................................................................................................................................................... 4 FIFO Programmability .............................................................................................................................................4 FIFO Access ........................................................................................................................................................... 4 Transmit FIFO ...................................................................................................................................................... 5 Receive FIFO ...
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June 2001 Description PLL OSCILLATOR DPLS DMNS USB V XCVR USS-820D is a USB device controller that provides a programmable bridge between the USB and a local microprocessor bus available in two package types: 44-pin ...
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USB Device Controller Description (continued) Protocol Layer The protocol layer manages the interface between the SIE and FIFO control blocks. It passes all USB OUT and SETUP packets through to the appropriate FIFO the responsibility of firmware to ...
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June 2001 Description (continued) FIFO Access (continued) Transmit FIFO The transmit FIFOs are circulating data buffers that have the following features: Support up to two separate data sets of variable sizes (dual-packet mode). I Include byte counter register for storing ...
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USB Device Controller Description (continued) FIFO Access (continued) Receive FIFO The receive FIFOs are circulating data buffers that have the following features: Support up to two separate data sets of variable sizes (dual-packet mode). I Include byte count register that ...
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June 2001 Pin Information V 1 DDA XTAL1 2 XTAL2 DDT DMNS 5 DPLS SST Figure 4. USS-820D Pin Diagram (44-Pin MQFP DDA XTAL1 ...
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USB Device Controller Pin Information (continued) Table 2. Pin Descriptions 44-Pin MQFP 48-Pin TQFP (USS-820D) (USS-820TD 12, 11, 10, 9, 13, 12, 11, 8 10, 9 ...
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June 2001 Pin Information (continued) Table 2. Pin Descriptions (continued) 44-Pin MQFP 48-Pin TQFP (USS-820D) (USS-820TD 35, 36, 37, 38, 39, 40, 38, 39, 41, 41, ...
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USB Device Controller Register Timing Characteristics Table 4. Register Access Timing—Special Function Register (SFR) Read Symbol tRDASU Read Address Setup Time (starts before the trailing edge of RDN or IOCSN, whichever is first) tRDAHD Read Address Hold (starts after the ...
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June 2001 Register Timing Characteristics Table 5. Register Access Timing—Special Function Register (SFR) Write Symbol tWRASU Write Address Setup Time (starts before the trailing edge of WRN or IOCSN, whichever is first) tWRAHD Write Address Hold (starts after the trailing ...
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USB Device Controller Register Interface The USS-820D is controlled through an asynchronous, read/write register interface. Registers are addressed via the A[4:0] pins, and control is provided through the RDN, WRN, and IOCSN pins. Reserved bits of registers must always be ...
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June 2001 Register Interface (continued) Table 7. Special Function Registers (By Address) Address Register 00H* TXDAT Transmit FIFO Data Register 01H* TXCNTL Transmit FIFO Byte-Count Low Register 02H* TXCNTH Transmit FIFO Byte-Count High Register 03H* TXCON USB Transmit FIFO Control ...
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USB Device Controller Register Interface (continued) Special Firmware Action for Shared Register Bits Since the USS-820D registers are not bit-addressable and contain several bits that may be written by either firmware or hardware (shared bits), special care must be taken ...
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June 2001 Register Interface (continued) In this case, the SBI/SBI1 bit will be set even though there is no corresponding data set present in the receive FIFO. Therefore, firmware must be prepared to service a receive done interrupt where no ...
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USB Device Controller Register Interface (continued) Register Descriptions Table 11. Serial Bus Interrupt Enable Register (SBIE)—Address: 16H; Default: 0000 0000B This register enables and disables the receive and transmit done interrupts for function endpoints 0 through 3. Bit 7 Bit ...
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June 2001 Register Interface (continued) Table 13. Serial Bus Interrupt Register (SBI)—Address: 14H; Default: 0000 0000B This register contains the USB function’s transmit and receive done interrupt flags for nonisochronous endpoints. These bits are never set for isochronous endpoints. Bit ...
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USB Device Controller Register Interface (continued) Table 14. Serial Bus Interrupt 1 Register (SBI1)—Address: 15H; Default: 0000 0000B This register contains the USB function’s transmit and receive done interrupt flags for nonisochronous endpoints. These bits are never set for isochronous ...
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June 2001 Register Interface (continued) Table 15. Start of Frame High Register (SOFH)—Address: 0FH; Default: 0000 0000B This register contains isochronous data transfer enable and interrupt bits and the upper 3 bits of the 11-bit time stamp received from the ...
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USB Device Controller Register Interface (continued) Table 16. Start of Frame Low Register (SOFL)—Address: 0EH; Default: 0000 0000B This register contains the lower 8 bits of the 11-bit time stamp received from the host. Bit 7 Bit 6 Bit 5 ...
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June 2001 Register Interface (continued) Table 18. Endpoint Control Register (EPCON)—Address: 0BH; Default: Endpoint 0 = 0011 0101B; Others = 0001 0000B This SFR configures the operation of the endpoint specified by EPINDEX. This register is endpoint indexed. Bit 7 ...
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USB Device Controller Register Interface (continued) Table 19. Endpoint Transmit Status Register (TXSTAT)—Address: 0CH; Default: 0000 0000B This register contains the current endpoint status of the transmit FIFO specified by EPINDEX. This register is endpoint indexed. Bit 7 Bit 6 ...
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June 2001 Register Interface (continued) Table 19. Endpoint Transmit Status Register (TXSTAT)—Address: 0CH; Default: 0000 0000B (continued) Bit Symbol 3 TXSOVW Transmit Data Sequence Overwrite Bit.* Writing this bit allows the value of the TXSEQ bit to ...
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USB Device Controller Register Interface (continued) Table 20. Endpoint Receive Status Register (RXSTAT)—Address: 0DH; Default: 0000 0000B This register contains the current endpoint status of the receive FIFO specified by EPINDEX. This register is an endpoint-indexed SFR. Bit 7 Bit ...
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June 2001 Register Interface (continued) Table 20. Endpoint Receive Status Register (RXSTAT)—Address: 0DH; Default: 0000 0000B (continued) Bit Symbol 2 RXVOID Receive Void (Read Only). Indicates a void condition has occurred in response to a valid OUT token. Receive void ...
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USB Device Controller Register Interface (continued) Table 21. Function Address Register (FADDR)—Address: 10H; Default: 0000 0000B This SFR holds the address for the USB function. During bus enumeration written by firmware with a unique value assigned by the ...
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June 2001 Register Interface (continued) Table 24. USB Transmit FIFO Control Register (TXCON)—Address: 03H; Default: 0000 0100B This register controls the transmit FIFO specified by EPINDEX. This register is endpoint indexed. Bit 7 Bit 6 Bit 5 TXCLR FFSZ1 FFSZ0 ...
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USB Device Controller Register Interface (continued) Table 25. Transmit FIFO Flag Register (TXFLG)—Address: 04H; Default: 0000 1000B These flags indicate the status of data packets in the transmit FIFO specified by EPINDEX. This register is endpoint indexed. Bit 7 Bit ...
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June 2001 Register Interface (continued) Table 25. Transmit FIFO Flag Register (TXFLG)—Address: 04H; Default: 0000 1000B (continued) Bit Symbol 7:6 TXFIF[1:0] Transmit FIFO Index Flags (Read Only) (continued). If MCSR.FEAT = 1: TXFIF bits are not visible to the host ...
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USB Device Controller Register Interface (continued) Table 25. Transmit FIFO Flag Register (TXFLG)—Address: 04H; Default: 0000 1000B (continued) Bit Symbol 0 TXOVF Transmit FIFO Overrun Flag (Read, Clear Only). This bit is set when an additional byte is written to ...
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June 2001 Register Interface (continued) Table 27. Receive FIFO Byte-Count High and Low Registers (RXCNTH, RXCNTL)—Address: RXCNTH = 07H, RXCNTL = 06H; Default: RXCNTH = 0000 0000B, RXCNTL = 0000 0000B High and low registers are in a two-register ring ...
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USB Device Controller Register Interface (continued) Table 28. Receive FIFO Control Register (RXCON)—Address: 08H; Default: 0000 0100B (continued) Bit Symbol 4 RXFFRC FIFO Read Complete. When set, the receive FIFO is released when a data set read is complete. Setting ...
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June 2001 Register Interface (continued) Table 29. Receive FIFO Flag Register (RXFLG)—Address: 09H; Default: 0000 1000B These flags indicate the status of the data packets in the receive FIFO specified by EPINDEX. This register is endpoint indexed. Bit 7 Bit ...
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USB Device Controller Register Interface (continued) Table 29. Receive FIFO Flag Register (RXFLG)—Address: 09H; Default: 0000 1000B (continued) Bit Symbol 7:6 RXFIF[1:0] Receive FIFO Index Flags (Read Only) (continued). For traceability, the RXFIF flags must be checked before and after ...
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June 2001 Register Interface (continued) Table 29. Receive FIFO Flag Register (RXFLG)—Address: 09H; Default: 0000 1000B (continued) Bit Symbol 0 RXOVF Receive FIFO Overrun Flag (Read, Clear Only). This bit is set when the SIE writes an additional byte to ...
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USB Device Controller Register Interface (continued) Table 30. System Control Register (SCR)—Address: 11H; Default: 0000 0000B This register controls the FIFO mode, IRQ mask, and IRQ mode selection. Bit 7 Bit 6 Bit 5 IRQPOL RWUPE IE_SUSP Bit Symbol 7 ...
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June 2001 Register Interface (continued) Table 31. System Status Register (SSR)—Address: 12H; Default: 0000 0000B This register allows control and monitoring of the USB suspend and reset events. Bit 7 Bit 6 Bit 5 — — Bit Symbol 7:5 — ...
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USB Device Controller Register Interface (continued) Table 33. Suspend Power-Off Locking Register (LOCK)—Address: 19H; Default: 0000 0001B This register contains the control and status which enables the USS-820D locking mechanism. This feature protects the internal register set from being corrupted ...
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June 2001 Register Interface (continued) Table 36. Miscellaneous Control/Status Register (MCSR)—Address: 1CH; Default: 0000 0000B (44-Pin MQFP—USS-820D) 0001 0000B (48-Pin TQFP—USS-820TD) This register contains miscellaneous control and status bits. Bit 7 Bit 6 Bit 5 RWUPR INIT SUSPS R R ...
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USB Device Controller Register Interface (continued) Table 37. Data Set Available (DSAV)—Address: 1DH; Default: 0000 0000B This register contains receive/transmit data set available bits. Bit 7 Bit 6 Bit 5 RXAV3 TXAV3 RXAV2 R R Bit Symbol 7 RXAV3 Receive/Transmit ...
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June 2001 Interrupts Figure 8 describes the device interrupt logic. Each of the indicated USB events are logged in a status register bit. Each status bit has a corresponding enable bit that allows the event to cause an interrupt. Interrupts ...
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USB Device Controller Firmware Responsibilities for USB SETUP Commands All SETUP commands are passed through from the USB host to the corresponding receive FIFO (assuming no data transfer errors). Firmware must interpret and execute each command according to its USB ...
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June 2001 Firmware Responsibilities for USB SETUP Commands (continued) Firmware must keep track of the direction of data flow during a control transfer, and detect the start of the status stage by a change in that direction. For control OUT ...
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USB Device Controller Suspend and Resume Behavior (continued) During a suspend/resume sequence, the following sequence of events occurs: 1. Hardware Suspend Detect: The USS-820D detects a suspend request from the host on USB and noti- fies firmware. 2. Firmware Suspend ...
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June 2001 Suspend and Resume Behavior (continued) Firmware Suspend Initiate (continued) While the USS-820D is suspended, its internal regis- ters may still be read, presumably only in self-powered devices. The interface timing for such reads is different from register reads ...
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USB Device Controller Suspend and Resume Behavior (continued) Special Suspend Considerations for Bus- Powered Devices (continued) D[7:0], SOFN*: Bidirectional pins, forced to input I mode while suspended (assuming SSR.SUSPPO = 1). Their value will be determined by external logic, and ...
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June 2001 Application Notes 1. The RESET input must remain asserted for a minimum period of time after power is stable. If internal oscillator clocking mode is used, this time is t become stable. If external oscillator clocking mode is ...
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USB Device Controller Electrical Characteristics dc Characteristics Table 44. dc Characteristics (T A Parameter High-Z State Data Line Leakage Differential Receiver: Common-mode Range Sensitivity Single-ended Receiver: Low High Hysteresis Output Voltage: Low High Transceiver Capacitance Hysteresis (RESET and RWUPN only) ...
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June 2001 Electrical Characteristics Power Considerations The USB specification places current limits on bus-powered devices. The limit is tighter for a device that has not yet been configured. The tightest limit is for a suspended device. The current values listed ...
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USB Device Controller Electrical Characteristics Connection Requirements USB Transceiver Connection The physical connection of the USS-820D to the USB bus requires only minimal components to provide proper USB electrical terminations. Both DPLS and DMNS require 24 Ω ± 1% series ...
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June 2001 Electrical Characteristics Connection Requirements (continued) Oscillator Connection Requirements The USS-820D requires an internal 48 MHz clock that it creates from an internal 12 MHz clock via a 4X PLL. Two methods of clock generation may be used to ...
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USB Device Controller Outline Diagrams 44-Pin MQFP (USS-820D) Dimensions are in millimeters DETAIL A 0.80 TYP 1.60 REF 0.25 GAGE PLANE SEATING PLANE DETAIL A 52 13.20 ± 0.20 10.00 ± 0.20 PIN #1 IDENTIFIER ZONE 44 34 ...
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... PIN #1 IDENTIFIER ZONE DETAIL A DETAIL B 0.05/0.15 0.50 TYP Ordering Information Device Code USS820D-DB 44-Pin MQFP USS820TD-DB* 48-Pin TQFP * Due to size constraints for the 48-pin TQFP package, the device package will be marked USS82TC-DB instead of USS820TD-DB. Agere Systems Inc. 36 7.00 ± 0.20 9.00 ± 0.20 25 1.40 ± 0.05 1 ...
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USB Device Controller Appendix A. Special Function Register Bit Names Table 47. Alphabetical Listing of Special Function Register Bit Names Bit Name Register Table A[6:0] FADDR ADVRM TXCON ADVWM RXCON ARM RXCON ASOF SOFH ATM TXCON BC[7:0] RXCNTL BC[7:0] TXCNTL ...
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June 2001 Appendix B. USS-820D Register Map Table 48. USS-820D Register Map Register TXDAT TXCNTL TXCNTH TXCON TXCLR TXFFSZ[1:0] TXFLG TXFIF[1:0] RXDAT RXCNTL RXCNTH RXCON RXCLR RXFFSZ [1:0] RXFLG RXFIF[1:0] EPINDEX EPCON RXSTL TXSTL TXSTAT TXSEQ TXDSAM RXSTAT RXSEQ RXSETUP ...
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USB Device Controller Appendix C. Changes from USS-820/ USS-825 Revision Note: For Revision C, the USS-825B has been renamed USS-820TC. 1. Hardware revision register (REV) changed from 1.0 to 1.1. 2. From the USB system and firmware ...
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June 2001 Appendix C. Changes from USS-820/ USS-825 Revision 14. Remote-wake-up-remember condition is visible as a register bit (RWUPR). Register bit always reads a 0 unless FEAT = 1. RWUPR is MCSR[7]. 15. Additional/updated electrical characteristics related ...
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For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere ...