hi-3599pst Holt Integrated Circuits, Inc., hi-3599pst Datasheet - Page 3

• Manufacturer Part Number: hi-3599pst
• Description: Octal Arinc 429 Receivers With Label Recognition And Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

PIN DESCRIPTIONS
INSTRUCTIONS
Instruction op codes are used to read, write and configure the
HI-3598 & HI-3599. When
SCK pin shift an instruction op code into the decoder, starting with
the first rising edge. The op code is fed into the SI pin, most
significant bit first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 16-bit Control Register writes, 32-
bit self-test register writes or 128-bit writes to a channel’s label-
matching enable/disable memory.
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As in write instructions,
the data field bit-length varies with read instruction type.
Channel-specific instructions use the upper four bits to specify an
ARINC 429 receiver channel, 1-8 hex . The lower four bits specify
the op code, described in Table 1. The four channel assignment bits
RINA1-40 - RINA8-40 ARINC INPUT Alternate ARINC receiver positive input. Requires external 40K ohm resistor
RINB1-40 - RINB8-40 ARINC INPUT Alternate ARINC receiver negative input. Requires external 40K ohm resistor
Channel
FLAG1 - FLAG8
1h - 8h
1h - 8h
1h - 8h
1h - 8h
1h - 8h
ARINC
RINA1 - RINA8
RINB1 - RINB8
X
X
X
X
X
X
SIGNAL
ACLK
FLAG
VDD
GND
SCK
TX1
TX0
MR
SO
CS
SI
OP CODE
Ah - Fh
Hex
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
ARINC INPUT ARINC receiver positive input. Direct connection to ARINC 429 bus
ARINC INPUT ARINC receiver negative input. Direct connection to ARINC 429 bus
FUNCTION
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
CS
128 bits
128 bits
goes low, the next 8 clocks at the
32 bits
16 bits
16 bits
16 bits
32 bits
32 bits
FIELD
DATA
None
None
None
3.3V or 5.0V power supply
Chip 0V supply
Chip select. Data is shifted into SI and out of SO when
SPI Clock. Data is shifted into or out of the SPI interface using SCK
SPI interface serial data input
SPI interface serial data output
Master 1 MHz timing reference for the ARINC 429 receiver and transmitter
Goes high when ARINC 429 receiver FIFO is not empty (CR1=0), or full (CR1=1)
Logical OR of FLAG1 through FLAG8
ARINC 429 test word ONE state serial output pin
ARINC 429 test word ZERO state serial output pin
Hardware active high Master Reset. Clears all receivers and FIFOs.
Does not affect Control Register contents.
Instruction not implemented. No operation.
Load label values to label memory. The data field consists of 16, 8-bit labels.
If fewer than 16 labels are needed for the application, the memory must be
padded with redundant (duplicate) label values.
Read the contents of the label memory for this channel
Read an ARINC word from the receive FIFO for this channel. If the FIFO is empty
all zeros will be read
Load the specified channel’s Control Register and clear that channel’s FIFO
Read
Read the Status Register.
Master Reset (All channels)
Load the Self Test Register and send the test word to all receivers (High-speed data rate)
Load the Self Test Register and send the test word to all receivers (Low-speed data rate)
Instruction not implemented. No operation.
TABLE 1. DEFINED INSTRUCTIONS
HOLT INTEGRATED CIRCUITS
the specified channel’s Control Register
DESCRIPTION
HI-3598, HI-3599
3
Example:
are “don’t care” for instructions that are not channel-specific, such
as Master Reset.
CS
SCK
SI
DESCRIPTION
ie: Load channel 1 control register with 0232 hex
MSB
op code 14 hex
MSB
SPI INSTRUCTION FORMAT
7
ARINC 429
LSB MSB
Channel
6
CS
one SPI Instruction
5
is low
4
3
data field 0232 hex
Op Code
2
1
0
LSB
3598 3599
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LSB
Std
Std
-40
-40
X
X
X
X
X
X
X
X