at52br3224a ATMEL Corporation, at52br3224a Datasheet - Page 8
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at52br3224a
Manufacturer Part Number
at52br3224a
Description
At52br3224a 32-megabit Flash + 4-megabit/ 8-megabit Sram Stack Memory
Manufacturer
ATMEL Corporation
Datasheet
1.AT52BR3224A.pdf
(46 pages)
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TOGGLE BIT: In addition to Data Polling the device provides another method for determining
the end of a program or erase cycle. During a program or erase operation, successive
attempts to read data from the memory will result in I/O6 toggling between one and zero. Once
the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examin-
ing the toggle bit may begin at any time during a program cycle. Please see “Status Bit Table”
on page 13 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and V
status
PP
bit as shown in the algorithm in Figures 3 and 4 on page 12.
ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates
whether the program or erase operation has exceeded a specified internal pulse count limit. If
the status bit is a “1”, the device is unable to verify that an erase or a word program operation
has been successfully performed. If a program (Sector Erase) command is issued to a pro-
tected sector, the protected sector will not be programmed (erased). The device will go to a
status read mode and the I/O5 status bit will be set high, indicating the program (erase) opera-
tion did not complete as requested. Once the erase/program status bit has been set to a “1”,
the system must write the Product ID Exit command to return to the read mode. The
erase/program status bit is a “0” while the erase or program operation is still in progress.
Please see “Status Bit Table” on page 13 for more details.
V
STATUS BIT: The device provides a status bit on I/O3, which provides information
PP
regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage
on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 sta-
tus bit will be a “1”. Once the V
status bit has been set to a “1”, the system must write the
PP
Product ID Exit command to return to the read mode. On the other hand, if the voltage level is
high enough to perform a program or erase operation successfully, the V
status bit will out-
PP
put a “0”. Please see “Status Bit Table” on page 13 for more details.
SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre-
vents programming of data in the designated sectors once the feature has been enabled.
These sectors can contain secure code that is used to bring up the system. Enabling the lock-
down feature will allow the boot code to stay in the device while data in the rest of the device is
updated. This feature does not have to be activated; any sector’s usage as a write-protected
region is optional to the user.
At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector,
the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked
down, the contents of the sector is read-only and cannot be erased or programmed.
SECTOR LOCKDOWN DETECTION: A software method is available to determine if program-
ming of a sector is locked down. When the device is in the software product identification
mode (see “Software Product Identification Entry/Exit” sections on page 27), a read from
address location 00002H within a sector will show if programming the sector is locked down. If
the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program
lockdown feature has been enabled and the sector cannot be programmed. The software
product identification exit code should be used to return to standard operation.
AT52BR3224A(T)/3228A(T)
8
3338B–STKD–6/03