m36l0t7050t2 Numonyx, m36l0t7050t2 Datasheet - Page 14

• Manufacturer Part Number: m36l0t7050t2
• Description: 128 Mbit Multiple Bank, Multi-level, Burst Flash Memory And 32 Mbit 2mb X16 Psram, Multi-chip Package
• Manufacturer: Numonyx

Functional description
Table 2.
1. X = Don't care.
2. WAIT signal polarity is configured using the Set Configuration Register command. See the M58LT128HTB datasheet for
3. L
4. Depends on G
5. Should not be kept in this logic condition for a period longer than 1µs.
6. G
7. Power-Down mode can be entered from Standby state and all Data outputs are in High-Z. The Power-Down current and
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Flash Read
Flash Write
Flash Address
Latch
Flash Output
Disable
Flash Standby
Flash Reset
PSRAM Read
PSRAM Write
PSRAM Output
Disabled
PSRAM Standby
(Deselected)
PSRAM Power-
Down
details.
a. Write pulse is initiated by E1
b. G
data retention depend on the selection of Power-Down programming.
Operation
F
P
(7)
can be tied to V
can be V
P
(5)
stays V
Operating modes
(5)
(5)
IL
IL
F
during the Write operation if the following conditions are satisfied:
.
during the entire Write cycle.
IH
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
if the valid address has been previously latched.
F
Flash Memory must be disabled
V
V
Any Flash mode is allowed
V
G
X
X
X
IH
IH
IL
F
V
V
V
P
W
V
X
X
IH
IH
IH
(E1
IL
F
(1)
P
V
V
Controlled Write timing), or cycle time of the previous operation cycle is satisfied;
V
L
IL
IL
X
X
X
IL
F
(3)
(3)
RP
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
F
WAIT
Hi-Z
Hi-Z
Hi-Z
F
(2)
E1
V
V
V
V
V
V
V
V
X
IH
IL
IL
IL
IL
IL
IL
IL
Any PSRAM mode is allowed
P
PSRAM must be disabled
E2
V
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IH
IH
IL
P
V
V
V
V
V
V
V
V
G
IH
X
X
IH
IH
IH
IL
IL
IL
IL
P
(6)
W
V
V
V
V
V
V
V
V
X
X
M36L0T7050T2, M36L0T7050B2
IH
IH
IH
IH
IL
IL
IL
IL
P
LB
V
V
V
V
V
V
V
IH
IH
IH
IL
IL
IL
IL
P
, UB
X
X
V
V
V
V
V
V
V
IH
IH
IH
IL
IL
IL
IL
P
data out
Data Out or Hi-Z
data in
DQ0-
DQ7
Hi-Z
Hi-Z
Data Out
data out
Data In
data in
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
data out
data in
DQ15
DQ8-
Hi-Z
Hi-Z
(4)