lrs1382 Sharp Microelectronics of the Americas, lrs1382 Datasheet - Page 65
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lrs1382
Manufacturer Part Number
lrs1382
Description
Flash Memory
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LRS1382.pdf
(114 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LRS1382
Manufacturer:
SHARP
Quantity:
20 000
NOTES:
1. Bus operations are defined in Table 4.
2. First bus cycle command address should be the same as the second cycle address.
3. ID=Data read from identifier codes. (See Table 6 through Table 8).
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
Read Array
Read Identifier Codes/OTP
Read Query
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
Program
Page Buffer Program
Block Erase and (Page Buffer)
Block Erase and (Page Buffer)
Set Block Lock Bit
Clear Block Lock Bit
Set Block Lock-down Bit
OTP Program
Set Read Configuration Register
Set Partition Configuration Register
Program Suspend
Program Resume
X=Any valid address within the device.
PA=Address within the selected partition.
IA=Identifier codes address (See Table 6 through Table 8).
QA=Query codes address. Refer to Appendix of LH28F320BX/LH28F640BX series for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA=Address of OTP block to be read or programmed (See Figure 4).
RCRC=Read configuration register code presented on the addresses A
PCRC=Partition configuration register code presented on the address A
QD=Data read from query database. Refer to Appendix of LH28F320BX/LH28F640BX series for details.
SRD=Data read from status register. See Table 9 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
OD=Data to be programmed at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
N-1=N is the number of the words to be loaded into a page buffer.
configuration code, read configuration register code, partition configuration register code and the data within OTP block
(See Table 6 through Table 8).
The Read Query command is available for reading CFI (Common Flash Interface) information.
block can be erased or programmed when RST# is V
Command
Synchronous burst mode will be available for future device.
Appendix to Spec No.:MFM2-J13222
Cycles
Req’d
Bus
2
1
2
1
2
2
1
1
2
2
2
2
2
2
2
2
4
Table 5. Command Definitions
2,3,5,6
2,3,5,7
Notes
2,3,4
2,3,4
2,3,5
2,5,9
2,8,9
2,8,9
2,3,9
2,10
2,3
2,3
2,3
2
2
2
2
FUM00701
IH
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
.
(1)
First Bus Cycle
Model No.: LRS1382
Addr
RCRC
PCRC
WA
WA
BA
BA
BA
BA
OA
PA
PA
PA
PA
PA
PA
PA
X
(2)
0
-A
0
-A
(11)
15
15
.
.
Data
40H or
B0H
D0H
C0H
FFH
E8H
90H
98H
70H
50H
20H
30H
10H
60H
60H
60H
60H
60H
(3)
March 1, 2001
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Read
Read
Read
(1)
Second Bus Cycle
IA or OA ID or OD
Addr
RCRC
PCRC
WA
WA
QA
BA
BA
BA
BA
OA
PA
X
(2)
Rev. 2.20
Data
SRD
D0H
D0H
D0H
2FH
WD
01H
03H
04H
N-1
QD
OD
19
(3)