k4t1g084qa-zce60 Samsung Semiconductor, Inc., k4t1g084qa-zce60 Datasheet - Page 25
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k4t1g084qa-zce60
Manufacturer Part Number
k4t1g084qa-zce60
Description
1gb A-die Ddr2 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4T1G084QA-ZCE60.pdf
(28 pages)
19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less
of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.
21. tQH = tHP – tQHS, where:
22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate
mismatch between DQS / DQS and associated DQ in any given cycle.
23. tDAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up.
24. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during pre-
charge power-down, a specific procedure is required as described in DDR2 device operation
25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
26. ODT turn off time min is when the device starts to turn off ODT resistance.
27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Following figure shows a method to calculate the point when device is
no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical
as long as the calculation is consistent.
28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),
or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.
1G A-die DDR2 SDRAM
These notes are referenced in the “Timing parameters by speed grade” tables for DDR2-400/533 and DDR2-667.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
tWR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer.
tCK refers to the application clock period.
Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.
tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately,
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the half period jitter ( tJIT(HP))
DDR2 SDRAM
Rev. 1.1 Aug. 2005
value can be