k4t51043qg-hcf7 Samsung Semiconductor, Inc., k4t51043qg-hcf7 Datasheet - Page 16

• Manufacturer Part Number: k4t51043qg-hcf7
• Description: 512mb G-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

K4T51043QG
K4T51083QG
K4T51163QG
10.0 IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Symbol
IDD4W
IDD2Q
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD5B
IDD0
IDD1
IDD6
IDD7
Operating one bank active-precharge current;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RC = t RC (IDD), t RAS = t RASmin(IDD), t RCD =
t RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pat-
tern is same as IDD4W
Precharge power-down current;
All banks idle; t CK = t CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current;
All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE; Data
bus inputs are FLOATING
Precharge standby current;
All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
All banks open; t CK = t CK(IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
All banks open; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP
= t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RAS = t RAS-
max(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t CK = t CK(IDD); Refresh command at every t RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid com-
mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = t RCD(IDD)-1* t CK(IDD); t CK = t CK(IDD), t RC
= t RC(IDD), t RRD = t RRD(IDD), t FAW = t FAW(IDD), t RCD = 1* t CK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions
t CK = t CK(IDD), t RC = t RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Proposed Conditions
16 of 45
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
Normal
Low Power
Rev. 1.21 February 2008
DDR2 SDRAM
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes