k4d261638k Samsung Semiconductor, Inc., k4d261638k Datasheet - Page 12

• Manufacturer Part Number: k4d261638k
• Description: 128mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

9.3 AC INPUT OPERATING CONDITIONS
Note :
1. In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK’s crossing point.
2. For K4D261638J-LC50, V
K4D261638K
Recommended operating conditions(Voltage referenced to V
Note :
1. V
2. The value of V
3. For K4D261638J-LC50, V
9.4 AC OPERATING TEST CONDITIONS
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
Input Levels(V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Input High (Logic 1) Voltage; DQ
Input Low (Logic 0) Voltage; DQ
Clock Input Differential Voltage; CK and CK
Clock Input Crossing Point Voltage; CK and CK
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
IH
IX
/V
is expected to equal 0.5*V
IL
Parameter
)
Parameter
DD
DD
&
&
V
V
Output
DDQ
DDQ
= 2.375V to 2.7V.
= 2.375V to 2.7V.
DDQ
of the transmitting device and must track variations in the DC level of the same.
Symbol
(Fig. 1) Output Load Circuit
V
V
V
V
IH
ID
IL
IX
SS
Z0=50Ω
=0V, V
- 12 /19 -
C
0.5*V
LOAD
V
DD
REF
V
=2.5V+ 5%, V
=30pF
Min
0.7
REF
DDQ
-
+0.35
+0.35/V
0.50*V
-0.2
See Fig.1
Value
V
V
1.5
1.0
V
REF
tt
tt
=0.5*V
DDQ
R
REF
DDQ
T
=50Ω
Typ
-0.35
=2.5V+ 5%,T
-
-
-
-
DDQ
V
=0.5*V
REF
128M GDDR SDRAM
DDQ
0.5*V
(VDD=2.5V+ 5%
V
V
REF
A
DDQ
=0 to 65°C)
Max
DDQ
-
-0.35
+0.6
+0.2
Rev. 1.3 July 2007
V/ns
Unit
V
V
V
V
V
*2
Unit
, TA= 0 to 65°C)
V
V
V
V
Note
1
Note
1
2