k4s640832k Samsung Semiconductor, Inc., k4s640832k Datasheet
k4s640832k
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k4s640832k Summary of contents
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... K4S640832K K4S641632K 64Mb K-die SDRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4S640832K K4S641632K Revision History Revision Month Year 0.0 January 2005 - Target spec release 0.1 March 2005 - Change DC current 0.2 April 2005 - Delete bit organization for x4 0.3 July 2005 - Delete 7ns speed bin 1.0 September 2005 - Final spec release 1.1 February 2006 - Added 5ns speed bin for x16 ...
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... RoHS compliant for Pb-free Package GENERAL DESCRIPTION The K4S640832K / K4S641632K is 67,108,864 bits synchronous high data rate Dynamic RAM organized 2,097,152 words by 8 bits 1,048,576 words by 16 bits, fabricated with SAMSUNGcs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications ...
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... K4S640832K K4S641632K Package Physical Dimension #54 #1 0.10 MAX 0.004 0. 0.028 54Pin TSOP(II) Package Dimension #28 #27 22.62 MAX 0.891 22.22 r0.10 0.21 r0.05 0.875 0.008 r0.004 r0.002 +0.10 0.30 0.80 -0.05 0.004 0.0315 0.012 -0.002 Synchronous DRAM 0~8qC 0.25 TYP 0.010 +0.075 0.125 -0.035 +0.003 0.005 -0.001 1.00 1.20 r0.10 MAX 0.039 0.047 r0.004 0.05 MIN ...
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... K4S640832K K4S641632K FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE CS Samsung Electronics reserves the right to change products or specification without notice. * Data Input Register Column Decoder Latency & ...
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... K4S640832K K4S641632K PIN CONFIGURATION (Top view) x8 x16 DQ0 DQ0 V V DDQ DDQ DQ1 N.C DQ2 DQ1 V V SSQ SSQ DQ3 N.C DQ4 DQ2 V V DDQ DDQ DQ5 N.C DQ6 DQ3 V V SSQ SSQ DQ7 N LDQM N CAS CAS RAS RAS ...
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... K4S640832K K4S641632K ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... CC4 (Burst mode) Refresh current I t CC5 Self refresh current I CKE d0.2V CC6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S640832K-T(U)C 4. K4S640832K-T(U)L 5. Unless otherwise noted, input swing IeveI is CMOS 70qC for x8) A Test Condition Burst length = 1 t (min) t ...
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... K4S640832K K4S641632K DC CHARACTERISTICS (x16) (Recommended operating condition unless otherwise noted, T Parameter Symbol Operating current I CC1 (One bank active Precharge standby current in CC2 power-down mode I PS CC2 I N CC2 Precharge standby current in non power-down mode I NS CC2 I P CC3 Active standby current in ...
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... K4S640832K K4S641632K AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200: Output 30pF 870: (Fig output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) ...
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... K4S640832K K4S641632K AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3 Output data hold time CAS latency=2 CLK high pulse width CLK low pulse width Input setup time ...
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... K4S640832K K4S641632K IBIS SPECIFICATION I Characteristics (Pull-up) OH 200MHz/133MHz 200MHz/133MHz Voltage Min (V) I (mA) I (mA) 3.45 - 3.30 - -19.11 3.00 -0.35 -51.87 2.70 -3.75 -90.44 2.50 -6.65 -107.31 1.95 -13.75 -137.9 1.80 -17.75 -158.34 1.65 -20.55 -173.6 1.50 -23.55 -188.79 1.40 -26.2 -199.01 1.00 -36.25 -241.15 0.20 -46.5 -351.68 I Characteristics (Pull-down) OL 200MHz/133MHz 200MHz/133MHz Voltage Min Max (V) I (mA) I (mA) 3.45 43.92 155.82 3.30 - 3.00 43.36 153.72 1.95 41.20 148.40 1.80 40.56 146.02 1.65 39.60 141.75 1.50 38.40 136.08 1.40 37.28 131.39 1.00 30.08 105.84 0.85 26.64 93.66 0.65 21.52 75.25 0.40 14.16 49.14 200MHz/133MHz Pull-up 0 0.5 0 Max -100 -1 ...
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... K4S640832K K4S641632K V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) DD 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) SS -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 Synchronous DRAM Minimum V clamp current DD (Referenced Voltage I (mA) Minimum V clamp current -10 -20 -30 -40 -50 -60 Voltage I (mA) Rev ...
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... K4S640832K K4S641632K SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Entry Refresh Self refresh Exit Bank active & row addr. Read & Auto precharge disable column address Auto precharge enable Write & Auto precharge disable column address Auto precharge enable ...