k4s51163pf Samsung Semiconductor, Inc., k4s51163pf Datasheet

k4s51163pf

Manufacturer Part Number

k4s51163pf

Description

8m X 16bit X 4 Banks Mobile-sdram

Manufacturer

Samsung Semiconductor, Inc.

Datasheet

1.K4S51163PF.pdf (12 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

k4s51163pf-PF75

Manufacturer:

SEC

Quantity:

2 641

Current page: 1 of 12
Download datasheet (115Kb)

K4S51163PF-Y(P)F

8M x 16Bit x 4 Banks Mobile-SDRAM

FEATURES

• 1.8V power supply.

• LVCMOS compatible with multiplexed address.

• Four banks operation.

• MRS cycle with address key programs.

• EMRS cycle with address key programs.

• All inputs are sampled at the positive going edge of the system

• Burst read single-bit write operation.

• Special Function Support.

• DQM for masking.

• Auto refresh.

• 64ms refresh period (8K cycle).

• Commercial Temperature Operation (-25°C ~ 70°C).

• 1 /CS Support.

• 2Chips DDP 54Balls FBGA( -YXXX -Pb, -PXXX -Pb Free).

ORDERING INFORMATION

- F : Low Power, Commercial Temperature(-25°C ~ 70°C)

Notes :

1. In case of 40MHz Frequency, CL1 can be supported.

2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.

Address configuration

Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific

purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.

clock.

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

-. PASR (Partial Array Self Refresh).

-. Internal TCSR (Temperature Compensated Self Refresh)

-. DS (Driver Strength)

K4S51163PF-Y(P)F75

K4S51163PF-Y(P)F90

K4S51163PF-Y(P)F1L

Organization

Part No.

32M x16

111MHz(CL=3)*1,66MHz(CL=2)

133MHz(CL=3),83MHz(CL=2)

111MHz(CL=3),83MHz(CL=2)

BA0,BA1

Bank

Max Freq.

GENERAL DESCRIPTION

rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits,

fabricated with SAMSUNG’s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock and I/O transactions are possible on every

clock cycle. Range of operating frequencies, programmable

burst lengths and programmable latencies allow the same

device to be useful for a variety of high bandwidth and high per-

formance memory system applications.

The K4S51163PF is 536,870,912 bits synchronous high data

A0 - A12

Row

Interface

LVCMOS

Mobile-SDRAM

Column Address

54 FBGA Pb

A0 - A9

September 2004

(Pb Free)

Package

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