ic42s16102-7tig ETC-unknow, ic42s16102-7tig Datasheet
ic42s16102-7tig
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ic42s16102-7tig Summary of contents
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... IC42S16102 Document Title 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM Revision History Revision No History 0A Initial Draft 0B This device improves output driving strength The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. ...
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... Copyright 2000, Integrated Circuit Solution Inc. 2 DESCRIPTION ICSI 's 16Mb Synchronous DRAM IC42S16102 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. ...
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... IC42S16102 60-BALL VF-BGA ( 16M SDRAM ) 7 A10 VDD A11 VSS PIN DESCRIPTIONS A0 - A10 Address A11 Bank Address DQ0 - DQ15 Data Input/Output CLK Clock CKE Clock Enable CS Chip Select Row Address Strobe RAS ...
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... IC42S16102 FUNCTIONAL BLOCK DIAGRAM CLK CKE COMMAND CS RAS DECODER CAS & WE CLOCK MODE A11 GENERATOR REGISTER A10 SELF A9 REFRESH REFRESH A8 CONTROLLER CONTROLLER A7 A6 REFRESH A5 COUNTER ROW ADDRESS LATCH 11 4 ROW ADDRESS 2048 BUFFER 2048 ROW ADDRESS BUFFER ...
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... IC42S16102 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage CC MAX V Maximum Supply Voltage for Output Buffer CCQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG DC RECOMMENDED OPERATING CONDITIONS ...
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... IC42S16102 DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level OH V Output Low Voltage Level OL I Operating Current (1, Precharge Standby Current CC (In Power-Down Mode Active Standby Current CC (In Non Power-Down Mode) ...
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... IC42S16102 AC CHARACTERISTICS (1,2,3) Symbol Parameter t 3 Clock Cycle Time Access Time From CLK ( CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH t Output LOW Impedance Time Output HIGH Impedance Time ...
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... IC42S16102 OPERATING FREQUENCY / LATENCY RELATIONSHIPS Symbol Parameter — Clock Cycle Time — Operating Frequency t CAS Latency CAC t Active Command To Read/Write Command Delay Time RCD t RAS Latency ( RAC RCD CAC t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ...
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... IC42S16102 COMMANDS Active Command CLK HIGH CKE CS RAS CAS WE A0-A9 A10 A11 Write Command CLK HIGH CKE CS RAS CAS WE A0-A9 A10 A11 No-Operation Command CLK HIGH CKE CS RAS CAS WE A0-A9 A10 A11 Notes: 1. A8-A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 Read Command CLK ...
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... IC42S16102 COMMANDS (cont.) Mode Register Set Command CLK HIGH CKE CS RAS CAS WE A0-A9 A10 A11 Self-Refresh Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 Clock Suspend Command CLK CKE BANK(S) ACTIVE CS RAS CAS WE NOP A0-A9 A10 A11 10 Auto-Refresh Command CLK HIGH CKE CS RAS CAS ...
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... MCD command execution. Active Command (CS, RAS = LOW, CAS, WE= HIGH) The IC42S16102 includes two banks of 4096 rows each. This command selects one of the two banks according to the A11 pin and activates the row selected by the pins A0 to A10. This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs ...
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... IC42S16102 Self-Refresh Command (CS, RAS, CAS, CKE = LOW HIGH) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. The self-refresh operation is started by dropping the CKE pin from HIGH to LOW. The self-refresh operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins ...
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... IC42S16102 COMMAND TRUTH TABLE (1,2) Symbol Command MRS Mode Register Set (3,4) REF Auto-Refresh (5) SREF Self-Refresh (5,6) PRE Precharge Selected Bank PALL Precharge Both Banks ACT Bank Activate (7) WRIT Write WRITA Write With Auto-Precharge READ Read (8) READA Read With Auto-Precharge BST Burst Stop (9) NOP ...
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... IC42S16102 OPERATION COMMAND TABLE Current State Command Idle DESL NOP BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Active DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Read DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Write DESL ...
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... IC42S16102 OPERATION COMMAND TABLE Current State Command Write With DESL Auto-Precharge NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Precharge DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Immediately DESL Following NOP Row Active BST READ/READA WRIT/WRITA ACT PRE/PALL ...
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... IC42S16102 OPERATION COMMAND TABLE Current State Command Write Recovery DESL With Auto- NOP Precharge BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Refresh DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Mode Register DESL Set NOP BST READ/READA WRIT/WRITA ACT PRE/PALL ...
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... IC42S16102 CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh Undefined Self-Refresh Recovery Self-Refresh Recovery Illegal (2) Illegal (2) Self-Refresh Self-Refresh Recovery Idle State After t Idle State After t Illegal Illegal Power-Down on the Next Cycle Power-Down on the Next Cycle Illegal Illegal Clock Suspend Termination on the Next Cycle ...
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... IC42S16102 TWO BANKS OPERATION COMMAND TRUTH TABLE Operation CS CS RAS CS RAS CAS RAS RAS CAS CAS WE CAS CS CS RAS CAS DESL H X NOP L H BST L H READ/READA L H WRIT/WRITA L H ACT L L PRE/PALL L L REF L L MRS L L Notes HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address 2 ...
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... IC42S16102 SIMPLIFIED STATE TRANSITION DIAGRAM REGISTER WRIT WRITE CKE_ CKE CLOCK WRITA SUSPEND CKE_ CKE WRITE WITH PRECHARGE POWER ON POWER APPLIED Automatic transition following the completion of command execution. Transition due to command input. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 (One Bank Operation) ...
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... The burst length field in Q reach their the mode register stipulates the number of data items input CC or output in sequence. In the IC42S16102 product, a burst length full page can be specified. See the table on the next page for details on setting the mode register. ...
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... IC42S16102 MODE REGISTER WRITE MODE LT MODE M11 M10 others Integrated Circuit Solution Inc. DR042-0A 01/18/2005 Burst Length Burst Type Latency Mode M7 Write Mode 0 Burst Read & Burst Write 0 Burst Read & Single Write ...
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... IC42S16102 BURST LENGTH AND COLUMN ADDRESS SEQUENCE Column Address Burst Length Full Page n n (256) Notes: 1. The burst length in full page mode is 256. 22 Address Sequence ...
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... IC42S16102 BANK SELECT AND PRECHARGE ADDRESS ALLOCATION Row X0 — X1 — X2 — X3 — X4 — X5 — X6 — X7 — X8 — X9 — X10 0 1 X11 0 1 Column Y0 — Y1 — Y2 — Y3 — Y4 — Y5 — Y6 — Y7 — Y8 — Y9 — Y10 0 1 Y11 0 1 Integrated Circuit Solution Inc. ...
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... IC42S16102 Burst Read The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data corresponding to this address is output in synchronization with the clock signal after the CAS latency period. Next, data corresponding to an address generated automatically by the device is output in synchronization with the clock signal ...
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... IC42S16102 Read With Auto-Precharge The read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge com- pletes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation ...
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... IC42S16102 Write With Auto-Precharge The write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation ...
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... IC42S16102 Interval Between Read Command A new command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command ...
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... IC42S16102 Interval Between Write and Read Commands A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read command was executed. The I/On pins must be placed in the HIGH impedance state at least one cycle before data is output during this operation ...
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... IC42S16102 Interval Between Read and Write Commands A read command can be interrupted and a new write command executed while the read cycle is in progress, i. e., before that cycle completes. Data corresponding to the new write command can be input at the point new write command is executed. To prevent collision between input ...
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... IC42S16102 Precharge The precharge command sets the bank selected by pin A11 to the precharged state. This command can be executed at a time t following the execution of an active RAS command to the same bank. The selected bank goes to the idle state at a time t following the execution of the ...
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... IC42S16102 Write Cycle Interruption Using the Precharge Command A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (t ) from the precharge command to the point WDL where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the CAS ...
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... The IC42S16102 can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IC42S16102 repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle ...
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... The IC42S16102 can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full page. The IC42S16102 repeats the operation starting at the 256th cycle with data input returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle ...
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... CAS latency, as soon as one of the U/LDQM pins goes HIGH, the corresponding externally applied input data will no longer be written to the device internal circuits. Subsequently, the corresponding input continues to be muted as long as that U/LDQM pin remains HIGH. The IC42S16102 will revert to accepting input as soon as CLK COMMAND UDQM LDQM ...
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... IC42S16102 Bank Active Command Interval When the selected bank is precharged, the period trp has elapsed and the bank has entered the idle state, the bank can be activated by executing the active command. If the other bank is in the idle state at that time, the active ...
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... IC42S16102 OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle CLK t CHI HIGH CKE RAS CAS A0- A10 BANK 0 & 1 A11 DQM HIGH I/O WAIT TIME t RP T=100 s < > PALL CAS latency = 2, 3 ...
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... IC42S16102 Power-Down Mode Cycle CLK t CHI t t CKS CK CKE t CKA RAS CAS A0- A10 BANK 0 & 1 BANK A11 BANK 1 BANK 0 DQM I < > PRE < > PALL CAS latency = 2, 3 Integrated Circuit Solution Inc. ...
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... IC42S16102 Auto-Refresh Cycle CLK t CHI CKS CK CKE RAS CAS A0- A10 BANK 0 & 1 A11 DQM I < > PALL CAS latency = < > < > REF REF Tm Tn ROW ...
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... IC42S16102 Self-Refresh Cycle CLK t CHI CKS CK CKE t CKA RAS CAS A0- A10 BANK 0 & 1 A11 DQM I < > PALL CAS latency = 2, 3 Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR042-0A 01/18/2005 ...
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... IC42S16102 Read Cycle CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > < ACT READ CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Read Cycle / Auto-Precharge CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > < > ACT ...
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... IC42S16102 Read Cycle / Full Page CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM I/O t RCD t RAS t RC (BANK 0) < > ...
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... IC42S16102 Read Cycle / Ping-Pong Operation (Bank Switching CLK t CHI t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM I/O t RRD (BANK RCD ...
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... IC42S16102 Write Cycle CLK t CHI CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Auto-Precharge CLK t CHI t t CKS t CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = full page Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Ping-Pong Operation CLK t CHI t t CKS t CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM I/O t RRD (BANK RCD (BANK 0) ...
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... IC42S16102 Read Cycle / Page Mode CLK t CHI t t CKS t CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Read Cycle / Page Mode; Data Masking CLK t CHI t t CKS t CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM I/O t RCD t RAS t RC < ...
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... IC42S16102 Write Cycle / Page Mode CLK t CHI CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Page Mode; Data Masking CLK t CHI t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < ...
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... IC42S16102 Read Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM t DS I/O t RCD t RAS t RC < ...
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... IC42S16102 Read Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Precharge Termination CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Read Cycle / Byte Operation CLK t CHI t t CKS t CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM I/O8-15 I/O0-7 t RCD t RAS t RC < ...
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... IC42S16102 Write Cycle / Byte Operation CLK t CHI CKS CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM I/O8-15 I/O0-7 t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD ...
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... IC42S16102 Read Cycle CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Read Cycle / Auto-Precharge CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Read Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM I/O t RCD (BANK 0) t RAS (BANK (BANK 0) < ...
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... IC42S16102 Read Cycle / Ping Pong Operation (Bank Switching CLK t CHI t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM I/O t RRD (BANK ...
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... IC42S16102 Write Cycle CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Auto-Precharge CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Full Page CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 3, burst length = full page Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Ping-Pong Operation (Bank Switching CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM I/O t RRD (BANK RCD ...
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... IC42S16102 Read Cycle / Page Mode CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Read Cycle / Page Mode; Data Masking CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 DQM I/O t RCD t RAS t RC < ...
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... IC42S16102 Write Cycle / Page Mode CLK t CHI t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 0 A11 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Page Mode; Data Masking CLK t CHI t t CKS CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK DQM t DS I/O t RCD ...
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... IC42S16102 Read Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Read Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Write Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS ROW A0- ROW A10 A11 BANK 0 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care ...
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... IC42S16102 Read Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM I/O8-15 I/O0-7 t RCD t RAS t RC < ...
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... IC42S16102 Write Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 A11 BANK 1 BANK 0 UDQM LDQM I/O8-15 I/O0-7 t RCD t RAS t RC < ...
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... IC42S16102 Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A9 ROW ROW A10 BANK 1 A11 BANK 0 DQM I ...
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... IC42S16102-6TI 400mil TSOP-2 IC42S16102-6TIG 400mil TSOP-2(Pb-free) IC42S16102-6BIG 60Ball VF-BGA(Pb-free) 7 IC42S16102-7TI 400mil TSOP-2 IC42S16102-7TIG 400mil TSOP-2(Pb-free) IC42S16102-7BIG 60Ball VF-BGA(Pb-free) 7F, NO. 106, SEC. 1, HSIN-TAI 5 HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. Integrated Circuit Solution Inc. HEADQUARTER: HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 ...