ic42s16160 ETC-unknow, ic42s16160 Datasheet - Page 5

• Manufacturer Part Number: ic42s16160
• Description: 4m X 16bit X 4 Banks 256-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16160
PIN FUNCTIONS
Integrated Circuit Solution Inc.
DR037-0A 9/05/2003
DQM, UDQM ,LDQM
RAS, CAS, WE
DQ0 to DQ15
V
BA0,BA1
V
DDQ
A0-A12
Symbol
DD
CKE
CLK
CS
,
,
V
V
SS
SSQ
Power Supply Pin
Power Supply Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
I/O Pin
Type
Function (In Detail)
Master Clock: Other inputs signals are referenecd to the CLK rising edge
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal
clock signals,device input buffers and output drivers. Deactivating the clock
provides PRECHARGE POWER-DOWN and SELF REFRESH operation
(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank).
Chip Select: CS enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS is registered
HIGH. CS provides for external bank selection on systems with multiple
banks. CS is considered part of the command code.
Command Inputs:
being entered.
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and AUTO PRECHARGE bit for READ/WRITE
commands, to select one location out of the memory array in the respective
bank. The row address is specified by RA0-RA12. The column address is
specified by CA0-CA8 (IC42S16160)
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Din Mask / Output Disable: When DQM is high in burst write, Din for the
current cycle is masked. When DQM is is high in burst read, Dout is
disable at the next but one cycle.
Data Input / Output: Data bus.
Power Supply for the memory array and peripheral circuitry.
Power Supply are supplied to the output buffers only.
RAS
,
CAS
and
WE
(along with CS) define the command
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