ic42s16400 ETC-unknow, ic42s16400 Datasheet - Page 26

• Manufacturer Part Number: ic42s16400
• Description: 1m X 16bit X 4 Banks 64-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16400
PRECHARGE TERMINATION
PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
When CAS latency is 2, the read data will remain valid until one clock after the precharge command.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
26
CAS latency=2
DQ
CAS latency=3
DQ
Command
command
CLK
T0
Read
Read
T1
RP
from the precharge command.
T2
Q0
T3
Q1
Q0
T4
PRE
PRE
Q2
Q1
T5
t
RP
Q2
Q3
Integrated Circuit Solution Inc.
T6
t
RP
ACT
Q3
Hi-Z
T7
Burst lengh= X
ACT
DR034-0E 12/02/2003
Hi-Z
T8