hb288032a6 Renesas Electronics Corporation., hb288032a6 Datasheet - Page 40
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hb288032a6
Manufacturer Part Number
hb288032a6
Description
Flash Ata Card -
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.HB288032A6.pdf
(66 pages)
- Current page: 40 of 66
- Download datasheet (213Kb)
HB2881000/800/640/448/320/256/192/160/128/096/064/032A6
Note: FR: Feature register
12. Device control register: This register is write only register, and it is used for controlling the card
interrupt request and issuing an ATA soft reset to the card.
bit7
bit
7 to 4
3
2
1
0
13. Drive Address register: This register is read only register, and it is used for confirming the drive status.
This register is provides for compatibility with the AT disk drive interface. It is recommended that this
register is not mapped into the host’s I/O space because of potential conflicts on bit7.
bit7
bit
7
6
5 to 2 nHS3-0 (Head Select3-0)
1
0
40
Name
1
SRST (Software ReSeT)
nIEN (Interrupt ENable)
0
Name
nWTG (WriTing Gate)
nDS1 (Idrive Select1)
nDS0 (Idrive Select0)
SC: Sector Count register
SN: Sector Number register
CY: Cylinder register
DR: DRV bit of Drive Head register
HD: Head Number of Drive Head register
LBA: Logical Block Address Mode Supported
Y: The register contains a valid parameter for this command.
N: The register does not contain a valid parameter for this command.
bit6
bit6
nWTG
bit5
bit5
nHS3
bit4
bit4
nHS2
Function
don't care
This bit is set to "1".
This bit is set to "1" in order to force the card to perform Task File
Reset operation. This does not change the Card Configuration
registers as a Hardware Reset does. The card remains in Reset
until this bit is reset to "0".
This bit is used for enabling -IREQ. When this bit is set to "0", -IREQ
is enabled. When this bit is set to "1", -IREQ is disabled.
This bit is set to "0".
Function
This bit is unknown
This bit is unknown
These bits is the negative value of Head Select bits (bit 3 to 0) in
Drive/Head register.
This bit is unknown
This bit is unknown
bit3
1
bit3
nHS1
bit2
SRST
bit2
nHS0
bit1
nIEN
bit1
nDS1
bit0
0
bit0
nDS0
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