k9f1g08u0m-y Samsung Semiconductor, Inc., k9f1g08u0m-y Datasheet
k9f1g08u0m-y
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Document Title 128M x 8 Bit / 64M x 16 Bit Revision History Revision No History 0.0 1. Initial issue 0.1 1. Iol(R/B) of 1.8V is changed. - min. value : 7mA --> 3mA - Typ. value : 8mA --> 4mA 2. AC parameter is changed. tRP(min.) : 30ns --> 25ns 3. A recovery time of minimum required before internal circuit gets ready for any command sequences as shown in Figure 17. ---> ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Document Title 128M x 8 Bit / 64M x 16 Bit Revision History Revision No History 0.7 Errata is added.(Front Page)-K9F1GXXQ0M tWC tWP tWH tRC tREH tRP tREA tCEA Specification 45 Relaxed value 80 0.8 1. The 3rd Byte ID after 90h ID read command is don’t cared. ...
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... Pin TSOP I ( 0.5 mm pitch) - K9F1G08U0M-VCB0/VIB0 48 - Pin WSOP I (12X17X0.7mm) - K9F1GXXX0M-PCB0/PIB0 48 - Pin TSOP I ( 0.5 mm pitch)- Pb-free Package - K9F1G08U0M-FCB0/FIB0 48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9F1G08U0M-V,F(WSOPI ) is the same device as K9F1G08U0M-Y,P(TSOP1) except package type. 3 FLASH MEMORY PKG Type TSOP1 TSOP1 TSOP1 WSOP1 ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M PIN CONFIGURATION (TSOP1) K9F1GXXX0M-YCB0,PCB0/YIB0,PIB0 X16 X8 N.C N.C 1 N.C N.C 2 N.C N.C 3 N.C N.C 4 N.C N.C 5 N.C N.C 6 R/B R N.C N.C 10 N.C N.C 11 Vcc Vcc 12 Vss Vss 13 N.C N.C 14 N.C N.C 15 CLE CLE 16 ALE ALE N.C N.C 20 N.C N.C 21 N.C 22 N.C N.C N.C 23 N.C N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M PIN CONFIGURATION (WSOP1) K9F1G08U0M-VCB0,FCB0/VIB0,FIB0 N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE N.C 20 N.C 21 DNU 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I) ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The (K9F1G08X0M) O pins float to high-z when the chip is deselected or when the outputs are disabled. ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Figure 1-1. K9F1G08X0M (X8) Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE PRE Figure 2-1. K9F1G08X0M (X8) Array Organization ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Figure 1-2. K9F1G16X0M (X16) Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE PRE Figure 2-2. K9F1G16X0M (X16) Array Organization ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Product Introduction The K9F1GXXX0M is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8(X8 device) or 1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or 1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056- word(X16 device) cache register are serially connected to each other ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F1GXXX0M-XCB0 Temperature Under Bias K9F1GXXX0M-XIB0 K9F1GXXX0M-XCB0 Storage Temperature K9F1GXXX0M-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M DC AND OPERATING CHARACTERISTICS Parameter Symbol Page Read with tRC=50ns, CE Operating Serial Access I =0mA OUT Current Program Erase Stand-by Current(TTL CE=V SB CE=V Stand-by Current(CMOS WP=PRE=0V/V Input Leakage Current Vcc(max Output Leakage Current ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M VALID BLOCK Parameter Symbol Valid Block Number NOTE : K9F1GXXX0M 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Program / Erase Characteristics Parameter Program Time Dummy Busy Time for Cache Program Number of Partial Program Cycles in the Same Page Block Erase Time t NOTE : 1. Max. time of depends on timing between internal program completion and data in CBSY AC Timing Characteristics for Command / Address / Data Input ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M NAND Flash Technical Notes Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig- nificant bit) pages of the block. Random page address programming is prohibited. ...
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... K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte(X8 device) or 1056word(X16 device) data registers are utilized as separate buffers for this operation and the system design gets more flexible ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M NOTE I/O Device I/Ox K9F1G08X0M(X8 device) I I/O 7 K9F1G16X0M(X16 device) I I/O 15 Command Latch Cycle CLE ALE I/Ox K9F1G16X0M : I must be set to "0" Address Latch Cycle t CLS CLE ALS ALE I/Ox K9F1G16X0M : I must be set to "0" ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Input Data Latch Cycle CLE ALS WC ALE I/Ox DIN 0 Serial Access Cycle after Read t CEA CE t REA RE I/ R/B NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Status Read Cycle CLE t CLS I/Ox K9F1G16X0M : I must be set to "0" t CLR t CLH WHR IR* 70h 21 FLASH MEMORY t CEA t CHZ RHZ* t REA t OH Status Output ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Read Operation CLE ALE RE I/Ox 00h Col. Add1 Col. Add2 Column Address R/B Read Operation (Intercepted by CE) CLE CE WE ALE RE I/Ox Col. Add2 00h Col. Add1 Column Address R/B t CLR 30h Dout N Row Add1 ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M FLASH MEMORY 23 ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Page Program Operation CLE ALE RE I/Ox Col. Add2 80h Co.l Add1 SerialData Column Address Input Command R Din Din Row Add1 Row Add2 10h N M Program Byte Row Address Serial Input Command ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M FLASH MEMORY 25 ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M FLASH MEMORY 26 ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M FLASH MEMORY 27 ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h Row Add1 Row Add2 Row Address R/B Auto Block Erase Erase Command Setup Command t t BERS WB D0h Busy Read Status Command 28 FLASH MEMORY 70h I/O 0 I/O =0 Successful Erase 0 I/O =1 Error in Erase ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Read ID Operation CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle K9F1G08Q0M K9F1G08D0M K9F1G08U0M K9F1G16Q0M K9F1G16D0M K9F1G16U0M ID Defintition Table Access command = 90H Description 1 st Byte Maker Code 2 nd Byte Device Code 3 rd Byte Don’t care ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M 4th ID Data ITEM Description 1KB Page Size 2KB (w/o redundant area ) Reserved Reserved 64KB Blcok Size 128KB (w/o redundant area ) 256KB Reserved Redundant Area Size 8 ( byte/512byte Organization x16 50ns 25ns Serial Access minimum Reserved Reserved FLASH MEMORY ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Device Operation PAGE READ Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the com- mand register along with four address cycles. In two consecutive read operations, the second one doesn’t need 00h command, which four address cycles and 30h command initiates that operation ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 30h 4Cycles Col Add1,2 & Row Add1,2 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112(X8 device) or words up to 1056(X16 device single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array(X8 device:1time/16byte ,X16 device:1time/8word) ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Figure 9. Random Data Input In a Page R/B I/Ox 80h Address & Data Input Col Add1,2 & Row Add1,2 Data Cache Program Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data regis- ters, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell ...
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... K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after com- pletion of the previous cycle, which can be expressed as the following formula ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address (X8 Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Power-On Auto-Read The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto- page read function ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M 300n 200n 100n 300n 200n 100n 300n 200n 100n Rp value guidance V (Max Rp(min, 1.8V part (Max Rp(min, 2.65V part (Max Rp(min, 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B pin. ...
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... K9F1G08Q0M K9F1G16Q0M K9F1G08D0M K9F1G16D0M K9F1G08U0M K9F1G16U0M Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hard- ware protection and is recommended to be kept at V required before internal circuit gets ready for any command sequences as shown in Figure 17 ...