m393t2863az3 Samsung Semiconductor, Inc., m393t2863az3 Datasheet - Page 17

• Manufacturer Part Number: m393t2863az3
• Description: Ddr2 Registered Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

Electrical Characteristics & AC Timing for DDR2-667/533/400
(Refer to notes for informations related to this table at the bottom)
Refresh Parameters by Device Density
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Timing Parameters by Speed Grade
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals tDQSQ
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
1GB, 2GB, 4GB Registered DIMMs
Refresh to active/Refresh command time
Average periodic refresh interval
Bin
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
(CL - tRCD - tRP)
(0 qC < T
Speed
tRCD
tRAS
tRP
tRC
OPER
Parameter
Parameter
< 95 qC; V
3.75
min
15
15
54
39
5
3
DDQ
DDR2-667(E6)
5 - 5 - 5
= 1.8V + 0.1V; V
tRFC
tREFI
70000
max
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH
tDS
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tQHS
tQH
tDQSS
8
8
8
Symbol
-
-
-
DD
85qC T
0qCdT
Symbol
= 1.8V + 0.1V)
tHP - tQHS
2*tAC min
min(tCL,
tAC min
3000
-0.25
tCH)
-400
0.45
0.45
min
-450
175
100
0.35
0.6
x
x
x
DDR2-667
CASE
CASE
3.75
min
15
15
55
40
5
-
DDR2-533(D5)
d 85qC
d 95qC
tAC max
tAC max
tAC max
4 - 4 - 4
+400
8000
max
0.55
0.55
0.25
+450
240
340
x
x
x
x
x
x
tHP - tQHS
2* tACmin
70000
min(tCL,
256Mb
max
tAC min
3750
-0.25
8
8
tCH)
0.45
0.45
7.8
3.9
-
-
-
-
min
-500
-450
225
100
0.35
75
0.6
x
x
x
DDR2-533
tAC max
512Mb
tAC max
tAC max
+500
+450
8000
105
max
0.55
0.55
0.25
7.8
3.9
300
400
x
x
x
x
x
x
min
15
15
55
40
5
5
-
DDR2-400(CC)
tHP - tQHS
2* tACmin
min(tCL,
tAC min
127.5
1Gb
5000
-0.25
tCH)
-600
-500
0.45
0.45
0.35
7.8
3.9
min
3 - 3 - 3
275
150
0.6
Rev. 1.2 Sep. 2005
x
x
x
DDR2-400
DDR2 SDRAM
2Gb
195
tAC max
tAC max
70000
7.8
3.9
tAC max
max
+600
+500
max
0.55
0.55
8000
0.25
350
450
8
8
-
-
-
-
x
x
x
x
x
x
327.5
4Gb
7.8
3.9
Units Notes
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Units
ns
ns
ns
ns
ns
ns
ns
Units
ns
Ps
Ps