m470t2953by3-ld5/cc Samsung Semiconductor, Inc., m470t2953by3-ld5/cc Datasheet - Page 15
![no-image](/images/no-image-200.jpg)
m470t2953by3-ld5/cc
Manufacturer Part Number
m470t2953by3-ld5/cc
Description
200pin Unbuffered Sodimm Based On 512mb B-die 64bit Non-ecc
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.M470T2953BY3-LD5CC.pdf
(19 pages)
256MB, 512MB, 1GB Unbuffered SODIMMs
CKE minimum pulse width (high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE asynchronously
drops LOW
Parameter
tCKE
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
tOIT
tDelay
Symbol
tIS+tCK +tIH
tAC(min)+2
tAC(min)+2
tAC(min)
tAC(min)
min
2.5
3
2
3
8
0
DDR2-533
tAC(max)+1
tAC(max)+1
2tCK+tAC(
tAC(max)+
2.5tCK+
max)+1
max
2.5
0.6
12
2
tIS+tCK +tIH
tAC(min)+2
tAC(min)+2
tAC(min)
tAC(min)
min
2.5
3
2
3
8
0
DDR2-400
Rev. 1.5 Aug. 2005
tAC(max)+1
tAC(max)+1
tAC(max)+
2tCK+tAC
(max)+1
2.5tCK+
DDR2 SDRAM
max
2.5
0.6
12
2
Units
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
Notes