m470t5267az3 Samsung Semiconductor, Inc., m470t5267az3 Datasheet - Page 2

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m470t5267az3

Manufacturer Part Number
m470t5267az3
Description
Ddr2 Unbuffered Sodimm
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
SODIMM
Table of Contents
1.0 DDR2 Unbuffered DIMM Ordering Information ......................................................................... 4
2.0 Features ........................................................................................................................................ 4
3.0 Address Configuration ................................................................................................................ 4
4.0 Pin Configurations (Front side/Back side) ................................................................................ 5
5.0 Pin Description ............................................................................................................................ 5
6.0 Input/Output Function Description ............................................................................................ 6
7.0 Functional Block Diagram : 4GB, 512Mx64 Module - M470T5267AZ(H)3 ............................... 7
8.0 Absolute Maximum DC Ratings .................................................................................................. 8
9.0 AC & DC Operating Conditions .................................................................................................. 8
10.0 IDD Specification Parameters Definition ............................................................................... 10
11.0 Operating Current Table : M470T5267AZ(H)3: 512Mx64 4GB Module ................................ 11
12.0 Input/Output Capacitance ....................................................................................................... 12
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533 ............................................ 12
14.0 Physical Dimensions : st.512Mbx8 based 512Mx64 Module (2 Ranks) .............................. 17
9.1 Recommended DC Operating Conditions (SSTL - 1.8)
9.2 Operating Temperature Condition
9.3 Input DC Logic Level
9.4 Input AC Logic Level
9.5 AC Input Test Conditions
13.1 Refresh Parameters by Device Density
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)
13.4 Timing parameters by speed grade (DDR2-533)
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Rev. 1.2 September 2008
DDR2 SDRAM

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