hys64t256022edl Qimonda, hys64t256022edl Datasheet

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... HYS64T256022EDL–[25F/2.5]–B; HYS64T256022EDL–[3/3S]–B; HYS64T256022EDL–3.7–B Revision History: 2006-11, Rev. 1.0 Page Subjects (major changes since last revision) All Adapted internet edition All Initial Document We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document ...

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... European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B • Programmable self refresh rate via EMRS2 setting • Programmable partial array refresh via EMRS2 settings • Average Refresh Period 7.8 µ 3.9µ ...

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... PC2–4200S–444–12–D0 1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T256022EDL–3.7–B, indicating Rev. “B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example “ ...

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... CAS 109 WE Address Signals 107 BA0 106 BA1 85 BA2 NC Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Table 6 and Table 7 respectively. The pin numbering is depicted in Pin Buffer Function Type Type I SSTL Clock Signals 2:0, Complement Clock Signals 2:0 ...

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... Data Signals 5 DQ0 7 DQ1 17 DQ2 19 DQ3 4 DQ4 6 DQ5 14 DQ6 16 DQ7 23 DQ8 25 DQ9 35 DQ10 37 DQ11 Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Pin Buffer Function Type Type I SSTL Address Bus 12:0 I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I ...

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... DQ44 142 DQ45 152 DQ46 154 DQ47 157 DQ48 159 DQ49 173 DQ50 175 DQ51 Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Pin Buffer Function Type Type I/O SSTL Data Bus 63:0 Data Input/Output pins I/O SSTL I/O SSTL I/O SSTL ...

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... DQS7 Data Mask Signals 10 DM0 26 DM1 52 DM2 67 DM3 130 DM4 147 DM5 170 DM6 185 DM7 Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Pin Buffer Function Type Type I/O SSTL Data Bus 63:0 I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL ...

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... SS 33,34,39,40,41,42,47,48,53, 54,59,60,65,66,71,72,77,78, 121,122,127,128,132,133,138,13 9,144,145,149,150,155,156,, 161,162,165,171,172,177, 178,183,184,187,190,193,196 Other Pins 114 ODT0 119 ODT1 NC 50,69,83,84,120,163,168 NC Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Pin Buffer Function Type Type I CMOS Serial Bus Clock I/O OD Serial Bus Data I CMOS Serial Address Select Bus 2:0 I CMOS AI — ...

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... OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Abbreviations for Pin Type Abbreviations for Buffer Type 10 Internet Data Sheet ...

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... Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Pin Configuration SO-DIMM (200 Pin) 11 Internet Data Sheet FIGURE 1 ...

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... When operating this product in the 85 ° °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Rating Min. ...

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... Under all conditions, must be less than or equal to DDQ V 2) Peak to peak AC noise on may not exceed ± 2% REF 3) Input voltage for any connector pin under test ≤ Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Symbol Values Min OPR T 0 CASE T – ...

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... DDR2 device can operate without a refresh command which is equal RAS.MAX Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Table 13 for DDR2–667D and Speed Grade Definition Speed Bins for DDR2–800 DDR2–800D –2.5F 5– ...

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... The output timing reference voltage level calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal RAS.MAX Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Speed Grade Definition Speed Bins for DDR2–667 DDR2–667C –3 4–4–4 Symbol Min. ...

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... The output timing reference voltage level calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal RAS.MAX Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Speed Grade Definition Speed Bins for DDR2–533C DDR2–533C –3.7 4–4–4 Symbol Min. ...

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... Mode register set command cycle time OCD drive mode output delay DQ/DQS output hold time from DQS Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Table 16 for DDR2–667D and Table 17 DRAM Component Timing Parameter by Speed Grade - DDR2–800 Symbol DDR2– ...

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... Thus, after any CKE transition, CKE may not transition from its valid level during the time period Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Symbol DDR2–800 Min. t — QHS t 0.9 RPRE t 0.4 RPST t 7 ...

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... Precharge command at Tm and Active command at nRP RP CK.AVG valid even if ( Tm) is less than 15 ns due to input clock jitter. Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B t refers to the application clock period. Example: For ( 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. DAL ...

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... Mode register set command cycle time OCD drive mode output delay DQ/DQS output hold time from DQS DQ hold skew factor Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules DRAM Component Timing Parameter by Speed Grade - DDR2–667 Symbol DDR2–667 Min. ...

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... RU stands for round up. WR refers to the tWR parameter stored in the MRS. For the division is not already an integer, round up to the next highest integer DDR2–533 at = 3.75 ns with programmed to 4 clocks Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Symbol DDR2–667 Min. t 0.9 RPRE t 0.4 RPST t 7.5 RRD ...

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... valid even if ( Tm) is less than 15 ns due to input clock jitter 32 lease two clocks ( independent of operation frequency. WTR CK Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]– [ps] / [ps] }, where WR is the value programmed in the EMR. RP CK.AVG JIT.PER JIT ...

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... Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Method for calculating transitions and endpoint Differential input waveform timing - t Differential input waveform timing - t 23 Internet Data Sheet FIGURE 2 FIGURE 3 and FIGURE 4 and ...

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... Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules DRAM Component Timing Parameter by Speed Grade - DDR2–533 Symbol DDR2–533 Min. ...

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... For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Symbol DDR2–533 Min. t — ...

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... AOFD t = 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT assumed, AOFD LOW and by counting the actual input clock edge. Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]– and ). and transitions occur in the same access time windows as valid data transitions ...

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... Both are measured from . Both are measured from AOFD 12 2 ns) after the clock edge that registered a first ODT HIGH if Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules ODT AC Character. and Operating Conditions for DDR2-533 Values Min. Max. ...

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... I List of Specification Tables: dd • Table 20 “IDD Measurement Conditions” on Page 28 • Table 21 “Definitions for IDD” on Page 29 • Table 22 “IDD Specification for HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B” on Page 30 Parameter Operating Current One bank Active - Precharge CK.MIN valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. ...

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... Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]– interval, CKE is LOW and CS is HIGH between valid RFC REFI of 85 ° ...

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... Fast: MRS(12)=0 5) Slow: MRS(12)=1 values are for 0°C ≤ and DD5D DD6 Case Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B I Specification for HYS64T256022EDL–[25F/2.5/3/3S/3.7]– ×64 ×64 ×64 2 Ranks 2 Ranks 2 Ranks –2.5 –3 –3S 1096 ...

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... Error Correction Support (non-ECC, ECC) 12 Refresh Rate and Type 13 Primary SDRAM Width 14 Error Checking SDRAM Width Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules SPD codes for HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B 2 GByte 2 GByte 2 GByte ×64 ×64 ×64 2 Ranks 2 Ranks 2 Ranks (×8) (× ...

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... DS.MIN t 35 [ns] DH.MIN t 36 [ns] WR.MIN t 37 [ns] WTR.MIN Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules 2 GByte 2 GByte 2 GByte ×64 ×64 ×64 2 Ranks 2 Ranks 2 Ranks (×8) (×8) (×8) PC2– PC2– PC2– 6400S– 6400S– ...

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... T 57 (DT7 Psi(ca) PLL 59 Psi(ca) REG ∆ (DTPLL) PLL Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B 2 GByte 2 GByte ×64 ×64 2 Ranks 2 Ranks (×8) (×8) PC2– PC2– 6400S– 6400S– 555 666 Rev. 1.2 Rev. 1.2 HEX ...

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... Product Type, Char 7 80 Product Type, Char 8 81 Product Type, Char 9 82 Product Type, Char 10 83 Product Type, Char 11 Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules 2 GByte 2 GByte 2 GByte ×64 ×64 ×64 2 Ranks 2 Ranks 2 Ranks (×8) (× ...

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... Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number 99 - 127 Not used 128 - Blank for customer use 255 Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules 2 GByte 2 GByte 2 GByte ×64 ×64 ×64 2 Ranks 2 Ranks 2 Ranks (× ...

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... Package Outlines Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Package Outline Raw Card D L-DIM-200-33 36 Internet Data Sheet FIGURE 5 ...

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... DRAM Technology 4 Memory Density per I/O [Mbit]; 1) Module Density 5 Raw Card Generation 6 Number of Module Ranks 7 Product Variations 8 Package, Lead-Free Status 9 Module Type Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Table 25 and for components in Table 64/128 512/ Values ...

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... Number of I/Os 7 Product Variations 8 Die Revision 9 Package, Lead-Free Status 10 Speed Grade Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules Values Coding –2.5F PC2–6400 5–5–5 –2.5 PC2–6400 6–6–6 –3 PC2–5300 4–4–4 –3S PC2– ...

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... Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.2 Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.3 ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 I Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Rev. 1.0, 2006-11 11172006-DXYK-2PPW HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules 39 Internet Data Sheet ...

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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...