hys64t256020hu Qimonda, hys64t256020hu Datasheet - Page 7
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hys64t256020hu
Manufacturer Part Number
hys64t256020hu
Description
240-pin Unbuffered Ddr2 Sdram Modules
Manufacturer
Qimonda
Datasheet
1.HYS64T256020HU.pdf
(61 pages)
- Current page: 7 of 61
- Download datasheet (2Mb)
2
2.1
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in
in columns Pin and Buffer Type are explained in
for non-ECC modules (×64) and
Rev. 1.32, 2006-09
03062006-5RK8-1X8J
Ball No.
Clock Signals
185
137
220
186
138
221
52
171
Control Signals
193
76
192
74
73
Address Signals
71
190
54
Name
CK0
CK1
CK2
CK0
CK1
CK2
CKE0
CKE1
NC
S0#
S1#
NC
RAS
CAS
WE
BA0
BA1
BA2
NC
Pin Configurations
Pin Configuration
Pin
Type
I
I
I
I
I
I
I
I
NC
I
I
NC
I
I
I
I
I
I
NC
Figure 2
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
for ECC modules (×72).
Function
Clock Signals 2:0, Complement Clock Signals 2:0
Clock Enable Rank 1:0
Note: 2 Ranks module
Not Connected
Note: 1 Rank module
Chip Select Rank 1:0
Note: 2 Ranks module
Not Connected
Note: 1 Rank module
Row Address Strobe
Column Address Strobe
Write Enable
Bank Address Bus 1:0
Bank Address Bus 2
Not Connected
Table 8
and
Table 9
7
respectively. The pin numbering is depicted in
Table 7
Unbuffered DDR2 SDRAM Modules
HYS[64/72]T256xxxHU–[3/…/5]–A
(240 pins). The abbreviations used
Pin Configuration of UDIMM
Internet Data Sheet
TABLE 7
Figure 1
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