hys64d32301eu-6-d Qimonda, hys64d32301eu-6-d Datasheet - Page 21

• Manufacturer Part Number: hys64d32301eu-6-d
• Description: 184-pin Unbuffered Double-data-rate Memory Modules
• Manufacturer: Qimonda

8) These parameters guarantee device timing, but they are not necessarily tested on each device.
9) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
Rev. 0.60, 2008-05
02142008-4Z51-SEDD
between
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on
performance (bus turnaround) degrades accordingly.
V
OH(ac)
and
V
OL(ac)
.
t
DQSS
.
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HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
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