atr0630 ATMEL Corporation, atr0630 Datasheet
atr0630
Related parts for atr0630
atr0630 Summary of contents
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... Supports NMEA, UBX Binary and RTCM Protocol for DGPS • Supports SBAS (WAAS, EGNOS, MSAS) • 4Hz Update Rate • Supports A-GPS (Aiding) • Excellent Noise Performance ® Processor Core ANTARIS4 Single-chip GPS Receiver ATR0630 Preliminary 4920B–GPS–06/06 ...
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... Due to the fully integrated design, just an RF SAW filter, a GPS XTAL (no TCXO) and blocking capacitors are required to realize a stand-alone GPS functionality. The ATR0630 includes a complete GPS firmware, licensed from u-blox AG, which performs the GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for external Flash- or ROM-memory ...
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... Architectural Overview 2.1 Block Diagram ATR0630 Block Diagram Figure 2-1. PUXTO PURF VDD18 VDDIO VDD_USB VDIG VCC1 VCC2 VBP TEST MO RF NRF XTO NXTO X NX RF_ON NSHDN NSLEEP XT_IN XT_OUT P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P14/NAADET1 P25/NAADET0 ...
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... Especially, due to its fast search engine and GPS accelerator, the ATR0630 only needs a GPS crystal (XTAL resonator for the integrated crystal oscillator of the ATR0630. This saves the considerable higher cost of a TCXO which is required for competi- tor’s systems. Also, as the powerful standard software is available in ROM, no external flash memory is needed ...
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... A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts. The ATR0630 includes full GPS firmware, licensed from u-blox AG, Switzerland. Features of the ROM firmware are described in software documentation available from u-blox AG, Switzerland. ...
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... Pin Configuration 3.1 Pinout Pinning BGA96 (Top View) Figure 3- Table 3-1. ATR0630 Pinout Pin Name BGA 96 Pin Type AGCO A4 Analog I/O CLK23 A8 Digital IN DBG_EN E8 Digital IN EGC D4 Digital IN GDIG C5 Supply GND A6 Supply GND A9 Supply GND B11 Supply GND F5 Supply GND H8 Supply ...
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... Table 3-1. ATR0630 Pinout (Continued) Pin Name BGA 96 Pin Type GNDA B4 Supply GNDA D2 Supply GNDA E1 Supply GNDA E2 Supply GNDA E3 Supply GNDA F1 Supply GNDA F2 Supply GNDA F3 Supply GNDA G1 Supply GNDA H1 Supply LDOBAT_IN D11 Supply LDO_EN C11 Digital IN LDO_IN E11 Supply LDO_OUT E12 Supply ...
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... Table 3-1. ATR0630 Pinout (Continued) Pin Name BGA 96 Pin Type P20 G7 Digital I/O P21 E6 Digital I/O P22 D10 Digital I/O P23 F8 Digital I/O P24 H7 Digital I/O P25 G5 Digital I/O P26 B6 Digital I/O P27 F7 Digital I/O P28 E7 Digital I/O P29 D5 Digital I/O P30 G12 Digital I/O P31 C10 Digital I/O PURF G4 Digital IN PURF H4 Digital IN PUXTO ...
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... Table 3-1. ATR0630 Pinout (Continued) Pin Name BGA 96 Pin Type (3) VDD_USB A10 Supply VDD18 H9 Supply VDD18 G11 Supply VDD18 F12 Supply VDD18 B9 Supply VDD18 E5 Supply (4) VDDIO B5 Supply VDDIO H5 Supply VDIG A5 Supply X A2 Analog OUT XT_IN A12 Analog IN XT_OUT B12 Analog OUT XTO ...
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... F[6-8], H[6,7] G8 NEEPROM DIGITAL IN GPS D7 STATUSLED DIGITAL OUT G7 TIMEPULSE DIGITAL OUT ATR0630 [Preliminary] 10 Active Level Pin Description/Comment - Leave open, internal pull down Low Reset input; open drain with internal pull-up resistor Low Shutdown output, connect to LDO_EN (C11) - Enable LDO18 Low Power-up output for GPS XTAL, connect to PUXTO (F4) ...
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... LDO_OUT SUPPLY LDOBAT D11 LDOBAT_IN SUPPLY D12 VBAT SUPPLY C12 VBAT18 SUPPLY 4920B–GPS–06/06 ATR0630 [Preliminary] Active Level Pin Description/Comment Low Active antenna short detection Input Low Active antenna detection Input - Active antenna power-on Output - Debug enable - Test data out - ...
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... GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0630 can be stored in an external non-volatile memory like EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is disabled (GPSMODE0 = 0) ...
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... Serial I/O Configuration The ATR0630 features a two-stage I/O-message and protocol-selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port ...
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... NMEA Port UBX Port Table 3-8. NMEA Port UBX Port Table 3-9. NMEA Port UBX Port Table 3-10. NMEA Port UBX Port ATR0630 [Preliminary] 14 Supported Messages at Setting Low Standard GGA, RMC NAV SOL, SVINFO MON EXCEPT Supported Messages at Setting Medium Standard GGA, RMC, GSA, GSV, GLL, VTG, ZDA ...
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... GGA, RMC, GSA, GSV User, Notice, Warning, Error USB Power Modes 0 USB device is bus-powered (maximum current limit 100 mA) (1) 1 USB device is self-powered (default ROM value) ATR0630 [Preliminary] USART2 UBX 57.6, Auto enabled UBX, NMEA, RTCM UBX NAV: SOL, SVINFO MON: EXCEPT User, Notice, Warning, Error ...
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... NANTSHORT) 3. Enable Open Circuit Detection via NAADET The antenna supervisor function may not be disabled by GPSMODE pin selection. If the antenna supervisor function is not used, please leave open ANTON, NANTSHORT and NAADET. ATR0630 [Preliminary] 16 Pin Usage of Active Antenna Supervisor Usage Meaning Active antenna short circuit detection ...
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... External Connections for a Working GPS System Figure 3-2. Example of an External Connection (ATR0630) LNA (optional) SAW ATR0610 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 GND +3V (see Power Supply) (see Power Supply) GND NC: Not connected 4920B–GPS–06/06 ...
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... P29/GPSMODE12/NPCS3 definitions in P30/AGCOUT0 Internal pull-down resistor; leave open. P31/RXD1 Internal pull-up resistor; leave open if serial interface is not used. ATR0630 [Preliminary] 18 12. “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “ ...
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... Connecting an Optional Serial EEPROM The ATR0630 offers the possibility of connecting an external serial EEPROM. The internal ROM firmware supports storing the configuration of the ATR0630 in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected to the ATR0630. The ATR0630’s 32-bit RISC processor accesses the external memory via SPI (serial peripheral inter- face). For best results, use a 32-Kbit 1.8V serial EEPROM such as Atmel’ ...
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... Power Supply The ATR0630 is supplied with six distinct supply voltages: • The power supplies for the RF part (VCC1, VCC2, VBP) within 2.7V to 3.3V. • VDIG, the 1.8V supply of the digital pins of the RF part (SIGHI, SIGLO and CLK23). VDIG should be connected to VDD18. • VDD18, the nominal 1.8V supply voltage for the core, the I/O pins, the memory interface and the test pins and all GPIO pins not mentioned in next item. • ...
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... NSHDN 1. 3.6V The ATR0630 contains a built in low dropout voltage regulator LDO18. This regulator can be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case, LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and 3.6V. ...
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... The RTC section will be initialized properly if VDD18 is supplied first to the ATR0630. If VBAT is applied first, the current consumption of the RTC and backup SRAM is undetermined. Connecting Example: Common Power Supplies for RF and Digital Part Using the Internal LDOs Figure 4-2. 2.7V to 3.3V NSHDN 1 µF (X7R) 1. 3.6V The USB Transceiver is disabled if VDD_USB < ...
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... VCC1 VCC2 VBP VDIG LDO_IN LDO_EN LDO_OUT VDD18 VDDIO 1 µF (X7R) LDOBAT_IN VBAT VBAT18 1 µF (X7R) VDDUSB ATR0630 [Preliminary] ATR0630 internal RF LDO18 ldoin ldoen ldoout Core 1.8V to 3.3V variable I/O domain LDOBAT ldobat_in vbat vbat18 VDD RTC backup memory USB SM and transceiver 23 ...
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... VCC1 VCC2 VBP VDIG LDO_IN NSHDN LDO_EN LDO_OUT VDD18 1 µF (X7R) VDDIO LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 1 µF (X7R) VDDUSB ATR0630 internal RF LDO18 ldoin ldoen ldoout Core 1.8V to 3.3V variable I/O domain LDOBAT ldobat_in vbat vbat18 VDD RTC backup memory USB SM and transceiver 4920B–GPS–06/06 ...
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... Crystals The ATR0630 only needs a GPS crystal (XTAL), but supports also TCXOs. The reference fre- quency is 23.104 MHz. By connecting an optional RTC crystal, different power modes are available. The reference frequency is 32.768 kHz. 5.1 GPS XTAL Figure 5-1. Figure 5-2. Note: The external series resistor R1 has to be selected depending on the typical value of the crystal ESR. Refer to the application note “ ...
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... Figure 5-3. Figure 5-4. ATR0630 [Preliminary] 26 Equivalent Application Examples Using a GPS TCXO (See TCXO 4 not connect TCXO 4 not connect Application Example Using an External Reference Frequency and Balanced Inputs (See Table 5-4 on page 27) 1 not B2 connect Table 5-3 on page ...
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... Over operating temperature range Operating temperature range DC coupled clipped sine wave Operating range Tolerable load capacitance Specification of an External Reference Signal for the Application Example Shown in Figure 5-4 on page 26 Comment Sine wave or clipped sine wave Voltage peak-to-peak ATR0630 [Preliminary] Min Typ Max 23.104 7.0 15.0 –40.0 +85.0 18.5 19.5 ...
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... RTC Oscillator Crystal Connection Figure 5-5. 32.768 kHz 50 ppm × can be derived from the crystal datasheet. Maximum value for load load ATR0630 [Preliminary] 28 XT_IN 32 kHz Crystal Oscillator 32.768 kHz clock XT_OUT ATR0630 internal RTC 4920B–GPS–06/06 ...
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... Digital input voltage P14, P16 to P27, P29, P31 Note: Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified. 7. Handling The ATR0630 is an ESD-sensitive device. The current ESD values are to be defined. Observe proper precautions for handling. 4920B–GPS–06/06 ATR0630 [Preliminary] Symbol ...
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... SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT external load allowed current is caused by outputs (pad output current as well as current across internal pull-up resistors) ATR0630 [Preliminary] 30 Pins Symbol V ...
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... If no current is caused by outputs (pad output current as well as current across internal pull-up resistors) 4920B–GPS–06/06 Pin = 2.2V = 1.0V = open A4 ext = 100 pF A4 ext F4, G4, H4 F4, G4, H4 LDO_OUT LDO_OUT VBAT18 VBAT18 ATR0630 [Preliminary] Symbol Min Typ Max N 6.6 VGA,min N 150 VGA,max f 250 3dB_AGC f 33 3dB_AGC V 0.9 2.3 ...
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... SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT external load allowed current is caused by outputs (pad output current as well as current across internal pull-up resistors) ATR0630 [Preliminary] 32 Pin Symbol CLK23 ...
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... If no current is caused by outputs (pad output current as well as current across internal pull-up resistors) 4920B–GPS–06/06 Pin = 2.2 mA, DP 0.2 mA, DP G9, H10, G10 A11, B10, C10, D10 E8, H11 F10, C8, F11, G12 C9 C9 C9, D9 ATR0630 [Preliminary] Symbol Min Typ Max V 0.3 OL,USB V 2.8 OH,USB I –1 +1 LEAK I 10 CAP R 0.7 1 ...
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... RTC, backup SRAM and LDOBAT Satellite acquisition Normal Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA All channels disabled Note: 1. Specified value only 11. Ordering Information Extended Type Number ATR0630-7KQY ATR0630-EK1 ATR0630-DK1 ATR0630 [Preliminary] 34 Package MPQ BGA96 3000 - Typ Unit (1) 0 ...
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... Primary datum C and seating plane are defined by the spherical crowns of the solder balls 4. The surface finish of the package shall be EDM CHARMILLE #24 - #27 5. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 5. Raw ball diameter: 0.4 mm ref. 4920B–GPS–06/06 ATR0630 [Preliminary 0. 0.15 m ...
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