ppc405gpr-3kb400z Applied Micro Circuits Corporation (AMCC), ppc405gpr-3kb400z Datasheet - Page 12

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ppc405gpr-3kb400z

Manufacturer Part Number
ppc405gpr-3kb400z
Description
Power Pc 405gpr Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
405GPr – Power PC 405GPr Embedded Processor
Serial Interface
IIC Bus Interface
General Purpose IO (GPIO) Controller
12
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow a wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
• Compliant with Philips® Semiconductors I
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V
• Two independent 4 x 1 byte data buffers
• Fifteen memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocol
• Programmable error recovery
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master
• 23 of 24 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
• Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three-
accesses
capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with:
stated if output bit is 1)
- 7 of 8 chip selects
- All 13 external interrupts
- All nine instruction trace pins
DD
IIC interface
2
C Specification, dated 1995
Revision 2.05 – March 24, 2008
Data Sheet
AMCC

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