ppc405gp-3ke266cz Applied Micro Circuits Corporation (AMCC), ppc405gp-3ke266cz Datasheet - Page 9

• Manufacturer Part Number: ppc405gp-3ke266cz
• Description: Power Pc 405gp Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

Revision 2.05 – August 19, 2008
On-Chip Memory (OCM)
The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the
processor core.
Features include:
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor
and local memory. This interface is compliant with version 2.2 of the PCI Specification.
Features include:
AMCC
• Low-latency access to critical instructions and data
• Performance identical to cache hits without misses
• Contents change only under program control
• Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is
• PCI bus frequency up to 66MHz
• 32-bit PCI address/data bus
• Power Management:
• Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI
• Buffering between PLB and PCI:
• Error tracking/status
• Supports PCI target side configuration
• Supports processor access to all PCI address spaces:
optional and can be disabled for systems which employ an external arbiter.
- Synchronous operation at 1/n fractions of PLB speed (n = 1 to 4) to 33MHz maximum
- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
- PCI Bus Power Management v1.1 compliant
- PCI target 64-byte write post buffer
- PCI target 96-byte read prefetch buffer
- PLB slave 32-byte write post buffer
- PLB slave 64-byte read prefetch buffer
- Single-byte PCI I/O reads and writes
- PCI memory single-beat and prefetch-burst reads and single-beat writes
- Single-byte PCI configuration reads and writes (type 0 and type 1)
- PCI interrupt acknowledge
- PCI special cycle
Data Sheet
405GP – Power PC 405GP Embedded Processor
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