peel22cv10aj-5 ETC-unknow, peel22cv10aj-5 Datasheet - Page 3

• Manufacturer Part Number: peel22cv10aj-5
• Description: Peel?22cv10a -5/-7/-10/-15/l-15/-25 Cmos Programmable Electrically Erasable Logic
• Manufacturer: ETC-unknow

Function Description
The PEEL22CV10A implements logic functions as
sum-of-products expressions in a programmable-
AND/fixed-OR logic array. User-defined functions
are created by programming the connections of in-
put signals into the array. User-configurable output
structures in the form of I/O macrocells further in-
crease logic flexibility.
Architecture Overview
The PEEL22CV10A architecture is illustrated in the
block diagram of Figure 2. Twelve dedicated inputs
and 10 I/Os provide up to 22 inputs and 10 outputs
for creation of logic functions. At the core of the
device is a programmable electrically-erasable AND
array which drives a fixed OR array. With this struc-
ture, the PEEL22CV10A can implement up to 10
sum-of-products logic expressions.
Associated with each of the 10 OR functions is an
I/O macrocell which can be independently pro-
grammed to one of 4 different configurations. The
programmable macrocells allow each I/O to create
sequential or combinatorial logic functions with
either active-high or active-low polarity.
AND/OR Logic Array
T h e
PEEL22CV10A (shown in Figure 3) is formed by
input lines intersecting product terms. The input
lines and product terms are used as follows:
132 product terms:
At each input-line/product-term intersection there is
an EEPROM memory cell which determines
whether or not there is a logical connection at that
intersection. Each product term is essentially a 44-
input AND gate. A product term which is connected
to both the true and compliment of an input signal
will always be FALSE, and thus will not effect the
OR function that it drives. When all the connections
on a product term are opened, a “don’t care” state
exists and that term will always be TRUE.
When programming the PEEL22CV10A, the device
programmer first performs a bulk erase to remove
the previous pattern. The erase cycle opens every
logical connection in the array. The device is then
configured to perform the user-defined function by
programming selected connections in the AND ar-
44 Input Lines:
24 input lines carry the true and complement
of the signals applied to the 12 input pins
20 additional lines carry the true and comple-
ment values of feedback or input signals from
the 10 I/Os
120 product terms (arranged in 2 groups of 8,
10, 12, 14 and 16) used to form logical sums
10 output enable terms (one for each I/O)
1 global synchronous present term
1 global asynchronous clear term
p r o g r a m m a b le
A N D
a r r ay
o f
t h e
3 - 53
ray. (Note that PEEL device programmers automat-
ically program the connections on unused product
terms so that they will have no effect on the output
function.)
Variable Product Term Distribution
The PEEL22CV10A provides 120 product terms to
drive the 10 OR functions. These product terms are
distributed among the outputs in groups of 8, 10,
12, 14 and 16 to form logical sums (see Figure 3).
This distribution allows optimum use of device re-
sources.
Programmable I/O Macrocell
The output macrocell provides complete control
over the architecture of each output. The ability to
configure each output independently permits users
to tailor the configuration of the PEEL22CV10A to
the precise requirements of their designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 4, consists
of a D-type flip-flop and two signal-select multiplex-
ers. The configuration of each macrocell is deter-
mined by the two EEPROM bits controlling these
multiplexers (refer to Table 1). These bits determine
output polarity and output type (registered or non-
registered). Equivalent circuits for the four macro-
cell configurations are illustrated in Figure 5.
Output Type
The signal from the OR array can be fed directly to
the output pin (combinatorial function) or latched in
the D-type flip-flop (registered function). The D-type
flip-flop latches data on the rising edge of the clock
and is controlled by the global preset and clear
terms. When the synchronous preset term is satis-
fied, the Q output of the register will be set HIGH at
the next rising edge of the clock input. Satisfying the
asynchronous clear term will set Q LOW, regardless
of the clock state. If both terms are satisfied simul-
taneously, the clear will override the preset.
Output Polarity
Each macrocell can be configured to implement
active-high or active-low logic. Programmable po-
larity eliminates the need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or
disabled under the control of its associated pro-
grammable output enable product term. When the
logical conditions programmed on the output enable
term are satisfied, the output signal is propagated
to the I/O pin. Otherwise, the output buffer is driven
into the high-impedance state.
Under the control of the output enable term, the I/O
pin can function as a dedicated input, a dedicated
output, or a bi-directional I/O. Opening every con-
nection on the output enable term will permanently
enable the output buffer and yield a dedicated out-
PEEL 22CV10A