mc5474hc163a ETC-unknow, mc5474hc163a Datasheet - Page 5

• Manufacturer Part Number: mc5474hc163a
• Description: 8-bit Serial-input/parallel-output Shift Reglster
• Manufacturer: ETC-unknow

High–Speed CMOS Logic Data
DL129 — Rev 6
INPUTS
A1, A2 (Pins 1, 2)
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and A2
inputs must be high, thereby allowing one input to be used as
a data–enable input. When only one serial input is used, the
other must be connected to V CC .
Clock (Pin 8)
shifts the data at each stage to the next stage. The shift
Serial Data Inputs. Data at these inputs determine the data
Shift Register Clock. A positive–going transition on this pin
CLOCK
A1 OR A2
Q
CLOCK
10%
50%
90%
10%
50%
90%
t r
t w
t PLH
t TLH
50%
Figure 1.
Figure 3.
t su
1/f max
VALID
t PHL
t f
50%
t THL
t h
SWITCHING WAVEFORMS
GND
V CC
PIN DESCRIPTIONS
V CC
GND
V CC
GND
3–5
register is completely static, allowing clock rates down to DC
in a continuous or intermittent mode.
OUTPUTS
Q A – Q H (Pins 3, 4, 5, 6, 10, 11, 12, 13)
ented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)
plied to this input resets all internal flip–flops and sets Out-
puts Q A – Q H to the low level state.
CLOCK
RESET
Parallel Shift Register Outputs. The shifted data is pres-
Active–Low, Asynchronous Reset Input. A low voltage ap-
Q
* Includes all probe and jig capacitance
t PHL
DEVICE
UNDER
Figure 4. Test Circuit
TEST
50%
Figure 2.
t w
t rec
50%
OUTPUT
50%
TEST POINT
MC54/74HC164A
C L *
GND
V CC
GND
V CC
MOTOROLA