ucn5841lw Allegro MicroSystems, Inc., ucn5841lw Datasheet - Page 5

• Manufacturer Part Number: ucn5841lw
• Description: Bimos Ii 8-bit Serial Input Latched Driver
• Manufacturer: Allegro MicroSystems, Inc.

5841
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
DATA IN
SERIAL
CLOCK
STROBE
OUTPUT
ENABLE
IN
SUB
Dwg. EP-021-8
Dwg. EP-010-4A
Dwg. EP-010-3
OUT
V
V
K
EE
DD
V DD
STROBE
OUTPUT
ENABLE
A. Minimum Data Active Time Before Clock Pulse
B. Minimum Data Active Time After Clock Pulse
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is held
high. Applications where the latches are bypassed (STROBE tied high)
will require that the ENABLE input be high during serial data entry.
disabled (OFF) without affecting the information stored in the latches or
shift register. With the ENABLE input low, the outputs are controlled by
the state of the latches.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
DATA IN
CLOCK
OUT
Serial Data present at the input is transferred to the shift register
Information present at any register is transferred to its respective
When the ENABLE input is high, all of the output buffers are
N
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
Output Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
C
B
D
E
F
G
Dwg. No. A-12,627
1.0 s