pdm41024sa10tty ETC-unknow, pdm41024sa10tty Datasheet

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pdm41024sa10tty

Manufacturer Part Number
pdm41024sa10tty
Description
1 Megabit Static Ram 128k X 8-bi
Manufacturer
ETC-unknow
Datasheet
Features
n
n
n
n
n
Functional Block Diagram
Rev. 3.3 - 4/09/98
High-speed access times
Com’l: 10, 12 and 15 ns
Ind’l: 12 and 15 ns
Low power operation (typical)
- PDM41024SA
- PDM41024LA
Single +5V ( 10%) power supply
TTL-compatible inputs and outputs
Packages
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
Plastic TSOP (I)- T
Active: 450 mW
Standby: 50 mW
Active: 400 mW
Standby: 25mW
CE1
CE2
WE
Addresses
OE
I/O
I/O
Control
0
7
A
A
16
0
Decoder
Input
Data
Control
Description
The PDM41024 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. Writing is
accomplished when the write enable (WE) and the
chip enable (CE1) inputs are both LOW and CE2 is
HIGH. Reading is accomplished when WE and CE2
remain HIGH and CE1 and OE are both LOW.
The PDM41024 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41024 comes in two versions:
the standard power version (SA) and the low power
version (LA). The two versions are functionally the
same and differ only in their power consumption.
The PDM41024 is available in a 32-pin plastic TSOP
(I), and a 300-mil and 400-mil plastic SOJ.
Column I/O
Memory
Matrix
• • • • •
1 Megabit Static RAM
PDM41024
128K x 8-Bit
1
10
11
12
1
2
3
4
5
6
7
8
9

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pdm41024sa10tty Summary of contents

Page 1

Features High-speed access times n Com’l: 10, 12 and 15 ns Ind’l: 12 and 15 ns Low power operation (typical PDM41024SA Active: 450 mW Standby PDM41024LA Active: 400 mW Standby: 25mW Single +5V ( 10%) ...

Page 2

Pin Configuration TSOP (I) 1 A11 A13 CE2 7 A15 8 Vcc A16 11 A14 A12 Pin Description Name Description ...

Page 3

Recommended DC Operating Condition Symbol Parameter V Supply Voltage CC V Supply Voltage SS Industrial Ambient Temperature Commercial Ambient Temperature DC Electrical Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO V Input Low Voltage IL ...

Page 4

Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT NOTE:1. This parameter is determined by device characterization but is not production tested. AC Test Conditions Input pulse levels Input rise and fall times Input timing reference levels Output ...

Page 5

Read Cycle No. 1 ADDR D OUT ( Read Cycle No. 2 ADDR CE1 CE2 OE D OUT AC Electrical Characteristics Description READ Cycle READ cycle time Address access time Chip enable access time Output hold ...

Page 6

Write Cycle No. 1 (Write Enable Controlled) ADDR CE2 CE1 OUT Write Cycle No. 2 (Write Enable Controlled) ADDR CE2 CE1 OUT NOTE: Output Enable (OE) is inactive (high ...

Page 7

Write Cycle No. 3 (Chip Enable Controlled) ADDR CE2 CE1 OUT NOTE: Output Enable (OE) is inactive (high) AC Electrical Characteristics Description WRITE Cycle WRITE cycle time Chip enable active time Address valid to end of ...

Page 8

Low V Data Retention Waveform CE1 CE2 IL Data Retention Electrical Characteristics (LA Version Only) for JEDEC Version Symbol Parameter V V for Retention Data Data Retention ...

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