hyb5117405bt-70 Infineon Technologies Corporation, hyb5117405bt-70 Datasheet
hyb5117405bt-70
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hyb5117405bt-70 Summary of contents
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Dynamic RAM 2k & 4k Refresh (Hyper Page Mode- EDO) Advanced Information 4 194 304 words by 4-bit organization • °C operating temperature • Performance: • t RAC RAS access time t CAC CAS ...
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... DRAM (access time 70 ns) P-SOJ-26/24 300 mil DRAM (access time 50 ns) P-SOJ-26/24 300 mil DRAM (access time 60 ns) P-SOJ-26/24 300 mil DRAM (access time 70 ns) P-TSOPII-26/24 300mil DRAM (access time 50 ns) P-TSOPII-26/24 300mil DRAM (access time 60 ns) P-TSOPII-26/24 300mil DRAM (access time 70 ns) ...
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... P-TSOPII-26/24 300 mil 26 Vss Vcc 25 I/O4 I/O1 24 I/O3 I/O2 23 CAS RAS A10 Vss VCC 4-EDO DRAM 1 26 Vss CAS Vss HYB 5117405 BJ/BT ...
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... Buffers(12) No. 1 Clock RAS Generator Block Diagram for HYB 5116405 Semiconductor Group HYB5116(7)405BJ/BT-50/-60/-70 & Data in Buffer 12 Row 12 Decoder Voltage Down Generator 4-EDO DRAM I/O1 I/O2 I/O3 I/O4 Data out Buffer 4 4 Column 10 Decoder Sense Amplifier I/O Gating 1024 x4 Memory Array 4096 4096x1024x4 VCC VCC (internal) ...
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... Buffers(11) No. 1 Clock RAS Generator Block Diagram for HYB 5117405 Semiconductor Group HYB5116(7)405BJ/BT-50/-60/-70 & Data in Buffer 11 Row 11 Decoder Voltage Down Generator 4-EDO DRAM I/O1 I/O2 I/O3 I/O4 Data out Buffer 4 4 Column 11 Decoder Sense Amplifier I/O Gating 2048 x4 Memory Array 2048 2048x2048x4 VCC VCC (internal) ...
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... I O(L) Vcc + 0.3V) I CC1 -50 ns version -60 ns version -70 ns version = t min CC2 I CC3 -50 ns version -60 ns version -70 ns version = t min 4-EDO DRAM Limit Values Unit Test min. max. 2.4 Vcc+0.5 V – 0.5 0.8 V 2.4 – V – 0.4 V – – – 100(120) mA – ...
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... CC5 I CC6 -60 ns version -70 ns version min.) I CC7 MHz Symbol 4-EDO DRAM Limit Values Unit Test min. max. – 70 (70) mA – 55 (55) mA – 45 (45) mA – – 100(120) mA – 90 (110) mA – 80 (100) ...
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... OEA 25 – 30 RAL t 0 – 0 RCS 0 – RCH t 0 – 0 RRH 0 – CLZ OFF 4-EDO DRAM Unit Note -60 -70 max. min. max. – 124 – ns – 50 – ns 10k 70 10k ns 10k 12 10k ns – 0 – ns – 10 – ns – ...
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... AWD t 10 – OEH 20 – t HPC 8 – – 27 CPA 5 – t COH 50 200k 60 t RAS t 27 – RHPC 4-EDO DRAM Limit Values -60 -70 max. min. max – 0 – 0 – 0 – 13 – 15 – 13 – 15 – 10 – 10 – 10 – ...
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... WRH 35 – t CPT 100k _ t RASS RPS - CHS t 10 – WTS 10 – t WTH t 30 – CHRT 4-EDO DRAM Limit Values -60 -70 max. min. max. 68 – 77 – 49 – 56 – 10 – 10 – 10 – 10 – 5 – 5 – 10 – 10 – 10 – ...
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... These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst ...
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... RC t RAS t CSH t t RSH RCD t CAS t RAD t RAL t CAH t ASC Column t t RAH RCS OEA t DZC t DZO t CAC t CLZ RAC 4-EDO DRAM CRP t ASR Row t RCH t RRH t CDD t ODD t OFF t OEZ Valid Data Out Hi Z WL1 ...
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... Write Cycle (Early Write) Semiconductor Group HYB5116(7)405BJ/BT-50/-60/- RAS t CSH t t RCD RSH t CAS t t RAD RAL t CAH t ASC Column t CWL t RAH t WCS WCH t RWL Valid Data 4-EDO DRAM CRP t ASR . Row WL2 ...
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... Write Cycle (OE Controlled Write) Semiconductor Group HYB5116(7)405BJ/BT-50/-60/- RAS t CSH t t RCD RSH t CAS t RAD t RAL t CAH t ASC Column t CWL t RAH t OEH t ODD t t DZO DZC OEZ Valid Data t CLZ t OEA Hi 4-EDO DRAM CRP t ASR Row t RWL Hi-Z WL3 . ...
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... RAH CAH t ASC Column t AWD t RAD t CWD t RWD RCS OEA t DZO t DZC t CLZ t CAC t RAC 4-EDO DRAM RWC RSH t CRP t CAS t ASR t CWL t RWL OEH Valid Data in t ODD t OEZ Data Out Row ...
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... ASC CAH CAH Column 2 Column 1 t RCS OES CPA t OEA t RAC COH CAC t CLZ Data Out 4-EDO DRAM t RHCP t RSH t t CAS CAS t RAL t t CAH ASC Column N t RRH t t CAC CAC CPA ...
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... ASC CAH ASC CAH Column 1 Column CWL t t WCS t WCH Data In 1 Data HYB5116(7)405BJ/BT-50/-60/- 4-EDO DRAM t RHCP t RSH t t CAS CAS t RAL t t ASC CAH Column N t RWL t CWL CWL t WCS t WCH WCH t ...
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... Hyper Page Mode (EDO) Late Write and Read-Modify Write Cycle Semiconductor Group HYB5116(7)405BJ/BT-50/-60/- 4-EDO DRAM 18 WL17 ...
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... V IH RAS CAS Address I/O (Outputs “H” or “L” RAS-Only Refresh Cycle Semiconductor Group HYB5116(7)405BJ/BT-50/-60/-70 t RAS t RAH ASR Row 4-EDO DRAM CRP t RPC t ASR HI-Z WL9 Row ...
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... OEZ CDD V IH I/O (Inputs ODD V OH I/O (Outputs OFF “H” or “L” CAS-Before-RAS Refresh Cycle Semiconductor Group HYB5116(7)405BJ/BT-50/-60/- RAS t CSR t CHR t WRP t WRH 4-EDO DRAM RPC HI-Z t CRP WL10 ...
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... RP t RAS t RSH t RCD t t WRP ASC t CAH Column t RRH t RCS OEA t DZC t DZO t CAC t CLZ t RAC Valid Data Out 21 HYB5116(7)405BJ/BT-50/-60/- 4-EDO DRAM RAS t t CRP CHR t t ASR WRH t CDD t ODD t OFF t OEZ Row HI-Z WL11 ...
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... Hidden Refresh Cycle (Early Write) Semiconductor Group HYB5116(7)405BJ/BT-50/-60/- RAS t t RCD RSH t RAD t ASC t CAH Column t WCS t t WRP WCH Valid Data HI 4-EDO DRAM RAS t t CHR CRP t ASR t WRH WL12 Row ...
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... CDD V I/O IH (Inputs ODD t OEZ V OH I/O (Outputs OFF “H” or “L” CAS before RAS Self Refresh Cycle Semiconductor Group HYB5116(7)405BJ/BT-50/-60/- RASS t CSR t WRP t WRH 4-EDO DRAM t RPS t CHS HI-Z WL13 t CRP ...
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... CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group CSR CHR t ASC Column t WRP t t WRH RCS t DZC t DZO t WCS WRP t WRH t DS HI-Z 24 HYB5116(7)405BJ/BT-50/-60/- 4-EDO DRAM t RAS t RSH t CAS t RAL t CAH CAC t OEA t ODD t OFF t t CLZ OEZ Data Out t RWL t CWL t ...
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... OEZ V OH I/O (Outputs “H” or “L” Test Mode Entry Semiconductor Group RPC CSR CHR t t ASR RAH Row t t WTS WTH t ODD HI-Z t CDD t OFF 25 HYB5116(7)405BJ/BT-50/-60/- 4-EDO DRAM RAS RP t RPC HI-Z t CRP WL15 ...
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... RAS refresh”, “RAS only refresh” or “Hidden refresh” can be used.Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other addresses are don’t care. Semiconductor Group HYB5116(7)405BJ/BT-50/-60/- 4-EDO DRAM 26 ...
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... M Block I Block Test 1 M Block A0C,A1C 1 M Block Normal 1 M Block I Block Test 1 M Block Block Diagram in Test Mode Semiconductor Group HYB5116(7)405BJ/BT-50/-60/- 4-EDO DRAM A0C,A1C A0C,A1C A0C,A1C A0C,A1C 27 Vcc Normal I/O 1 Test Vss Vcc Normal I/O 2 Test Vss ...
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... Package Outlines Plastic Package P-TSOPII-26/24 (300mil) (Thin small outline package, SMD) Semiconductor Group HYB5116(7)405BJ/BT-50/-60/- 4-EDO DRAM ...