k4h280438d Samsung Semiconductor, Inc., k4h280438d Datasheet - Page 8

• Manufacturer Part Number: k4h280438d
• Description: 128mb D-die X4/8 Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

128Mb D-die(x4/8) DDR SDRAM
1.2 Operating Frequencies
1. Key Features
1.1 Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
*CL : Cas Latency
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
-. Read latency 2, 2.5 (clock)
Speed @CL2.5
Speed @CL2
DLL jitter
Table 1. Operating frequency and DLL jitter
- B3(DDR333)
133Mhz
166Mhz
±0.7ns
- A2(DDR266A)
- 8 -
133MHz
133MHz
±0.75ns
- B0(DDR266B)
100MHz
133MHz
±0.75ns
REV. 0.3 Jan.31. 2001
- A0(DDR200)
100MHz
±0.8ns
-