ev1340 Enpirion, ev1340 Datasheet - Page 3

• Manufacturer Part Number: ev1340
• Description: 4a Synchronous Highly Integrated Dc-dc Ddr2/3/qdrtm Memory Termination Power Soc With Integrated Inductor
• Manufacturer: Enpirion

Pin Description
NAME
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VDDQOK
VSENSE
ENABLE
NC(SW)
EAOUT
FQADJ
EN_PB
AVIN1,
PGND
VDDQ
AVIN2
AGND
VOUT
VREF
POK
VFB
SW
Input and output power ground. Refer to layout section for specific layout requirements.
Regulated converter output. Decouple with output filter capacitor to PGND. Refer to layout section for
specific layout requirements
No Connect – these pins are internally connected to the common switching node of the internal MOSFETs.
They are not to be electrically connected to any external signal, ground, or voltage. Failure to follow these
guidelines may result in damage to the device.
These pins are internally connected to the common switching node of the internal MOSFETs. The anode
of a schottky diode needs to be connected to these pins. The cathode of the diode needs to be connected
to VDDQ.
In DDR applications the input to this pin is the DDR core voltage. This is the input power supply to the
power train which will be divided by two to create an output voltage that tracks with the input voltage
applied to this pin. Decouple with input capacitor to PGND. Refer to layout section for specific layout
requirements
This is the Device Enable pin. Floating this pin or a high level enables the device while a low level disables
the device.
Analog input voltage for the controller circuits. Each of these pins needs to be separately connected to the
3.3V input supply. Decouple with a capacitor to AGND.
POK is a logical AND of VDDQOK and the internally generated POK of the EV1340. POK is an open drain
logic output that requires an external pull-up resistor. POK is logic high when VOUT is within -10% to
+10% of VOUT nominal. This pin guarantees a logic low even when the EV1340 is completely un-
powered. This pin can sink a maximum 4mA. The pull-up resistor may be connected to a power supply
other than AVIN or VDDQ but the voltage should be <3.6Volts.
This is the quiet ground for the controller.
This is the Feedback input pin which is always active. A resistor divider connects from the output to
AGND. The mid-point of the resistor divider is connected to VFB. (A feed-forward capacitor and a resistor
are required across the upper resistor.) The output voltage regulates so as to make the VFB node voltage
= 600mV.
Optional Error Amplifier Output. Allows for customization of the control loop.
External voltage reference input. A resistor divider connects from VDDQ to AGND. The mid-point of the
resistor divider is connected to VREF. The resistor divider has to be chosen to make the voltage applied to
this pin 600mV. An optional capacitor (for soft start) may be connected from VREF to AGND.
This pin senses the output voltage.
The free running frequency of the internal oscillator may be reduced by connecting a suitable value resistor
from this pin to AGND.
Monotonic start-up with pre-bias is enabled by either pulling this pin high or letting it float. A logical low on
this pin will disable pre-bias mode operation.
This is an input pin to indicate the externally supplied VDDQ has settled sufficiently. This pin should be
tied to the VDDQ regulator POK output, or let float if unused.
FUNCTION
3
EV1340 Product Brief
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