rsc-4128 ETC-unknow, rsc-4128 Datasheet - Page 35

• Manufacturer Part Number: rsc-4128
• Description: Speech Recognition Processor
• Manufacturer: ETC-unknow

Instruction Opcode Operand 1
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
POP
PUSH
MOVY
MOVY
MOVD
Data Sheet
Instruction Set Opcodes and Timing Details
The RSC-4128 instruction set has 60 instructions comprising 13 move, 7 rotate/shift, 11 jump/branch, 13 register
arithmetic, 9 immediate arithmetic, and 7 miscellaneous instructions. All instructions are 3 bytes or fewer, and no
instruction requires more than 10 clock cycles (plus wait states) to execute. The column “Cycles” indicates the
number of clock cycles required for each instruction when operating with zero wait states. Wait states may be
added to lengthen all accesses to external addresses or to the internal ROM (but not internal SRAM). The column
“+Cycles/Waitstate” shows the number of additional cycles added for each additional wait state. Opcodes are in
HEX.
MOVE Group Instructions
Register-indirect instructions accessing code (MOVC), data (MOVX), technology (MOVY) or register (MOV) space
locations use an 8-bit operand (“@source” or “@dest”) to designate an SRAM register pointer to the 16-bit target
address. The “source” or “dest” indirect pointer register must be at an even address unless it is a 8-bit pointer
(indirect MOV). The LOW byte of the target address is contained at the pointer address, and the HIGH byte of the
target address is contained at the pointer address+1. Unless the flags register is the destination, the carry, sign,
and zero flags are not affected by MOV instructions.
* If register D6.Bit 5=1 (movX_4ws) and external read/write memory is selected by setting the “rw” bit (register D2.Bit4), MOVX
instructions have four additional wait states.
35
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
@dest
@dest--
dest_pair
dest
@dest
dest
dest
dest
dest
@dest
dest
dest
@dest
Operand 2
Source
Source
@source
#immed
@source
Source
@source
Source
@++source register to register data
Source
@source
source
source_pair register to register, direct,
P/N 80-0206-R
Description
register to register
register to register-indirect 3
register-indirect to register 3
immediate data to register 3
code space to register
register to code space
data space to register
register to data space
stack pop (source pre-
incremented)
register to register data
stack push (dest post-
decremented)
RAMY to register, indirect 3
Register to RAMY, indirect 3
16-bit MOV
Bytes Cycles +Cycles/Waitstate
3
3
3
3
3
3
3
3
8
5
5
6
4
7
8
7
10
9
7
7
7
© 2006 Sensory Inc.
3
3
3
3
4
4
4*
4*
3
3
3
3
3
RSC-4128