hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet

hi-6131pqtf

Manufacturer Part Number

hi-6131pqtf

Description

Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device

Manufacturer

QuickLogic Corp

Datasheet

1.HI-6131PQTF.pdf (271 pages)

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August, 2011

GENERAL DESCPIPTION

The 3.3V CMOS HI-613x device provides a complete

single- or multi-function interface between a host

processor and MIL-STD-1553B bus. Each IC contains

a Bus Controller (BC), a Bus Monitor Terminal (MT)

and two independent Remote Terminals (RTs). Any

combination of the contained 1553 functions can

be enabled for concurrent operation. The enabled

terminals communicate with the MIL-STD-1553 buses

through a shared on-chip dual bus transceiver and

external transformer. The user allocates 64K bytes of

on-chip static RAM between devices to suit application

requirements.

Two options are offered for host access to internal

registers and static RAM: The HI-6130 uses a 16-bit

parallel bus; the HI-6131 communicates with the host

via a 4-wire serial peripheral interface (SPI). Package

options vary, based on host interface I/O pin count:

Programmable interrupts provide terminal status to the

host processor. Circular data stacks in RAM have rollover

and programmable “level attained” interrupts. The HI-

613x can be configured for automatic self-initialization

after reset. A dedicated SPI port reads data from an

external serial EEPROM to fully configure registers and

RAM for any subset of one to four terminal devices.

FEATURES

DS6130 Rev. New

•

Device

HI-6130

HI-6131

Concurrent multi-terminal operation for one to

four MIL-STD-1553B functions: BC, MT and two

independent RTs.

Two host interface options: 16-bit parallel bus

for speed, or 4-wire SPI for smaller footprint and

interconnect wiring reduction.

64K bytes internal static RAM.

Autonomous terminal operation requires minimal

host intervention.

Shared 1553 bus interface reduces circuit

complexity and circuit board area.

Fully programmable Bus Controller with 28 op

code instruction set.

Host Interface Packages

16-bit parallel

4-wire SPI

100-pin PQFP

64-pin QFN

64-pin PQFP

HOLT INTEGRATED CIRCUITS

3.3V BC / MT / RT Multi-Terminal Device

www.holtic.com

MIL-STD-1553 / MIL-STD-1760

PIN CONFIGURATION (TOP)

•

WAIT / WAIT - 15

STR / OE - 11

R/W / WE - 16

RAMEDC - 8

RT1A_0 - 17

RT1A_1 - 18

RT1A_2 - 19

RT1A_3 - 21

RT1A_4 - 22

BCTRIG - 3

MODE - 10

MCLK - 13

VCC - 12

GND - 14

Bus Monitor can operate in dual-stack mode,

recording commands and data separately, with

16-bit or 48-bit time tagging.

Bus Monitor can record commands and data in

single-stack mode, using IRIG-106 Chapter 10

“packet body” format.

Single-stack Bus Monitor and can optionally

generate complete IRIG-106 data packets,

including full packet headers and trailers.

Independent 16-bit time tag counters and clock

sources for all terminals. The Bus Controller

and Monitor also have 32- and 48-bit time count

options, respectively.

64-Word Interrupt Log Buffer queues the most

recent 32 interrupts. Hardware-assisted interrupt

decoding quickly identifies interrupt sources.

RAM Error Detection/Correction option

Built-in self-test for protocol logic, digital signal

paths and internal RAM.

Optional self-initialization at reset uses external

serial EEPROM

±8kV ESD Protection (HBM, all pins).

Two temperature ranges: -40

-55

RoHS compliant lead-free option.

VCC - 1

GND - 2

MR - 20

D12 - 4

D13 - 5

D14 - 6

D15 - 7

A0 - 23

A1 - 24

A2 - 25

CE - 9

C to +125

C with optional burn-in.

HI-6130PQxF

HI-6130 / HI-6131

TOP VIEW

C to +85

C, or

75 - D1

74 - D0

73 - WPOL

72 - BTYPE

71 - BENDI

70 - TEST

69 - RT1LOCK

68 - MTSTOFF

67 - BCENA

66 - BUSA

65 - VCCP

64 - BUSA

63 - BUSB

62 - VCCP

61 - BUSB

60 - RT2ENA

59 - RT2A_0

58 - RT2A_1

57 - RT2A_2

56 - RT2A_3

55 - BWID

54 - A15

53 - A14

52 - A12

51 - A13

08/11

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