gvt71256zb18 ETC-unknow, gvt71256zb18 Datasheet - Page 11

• Manufacturer Part Number: gvt71256zb18
• Description: 256k Flow-through Sram
• Manufacturer: ETC-unknow

Note:
1. D(A
2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2#
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD# LOW.
4. R/W# is “Don’t Care” when the SRAM is bursting (ADV/LD# sampled HIGH). The nature of the burst access
5. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated
July 23, 1998
Rev. 7/98
GALVANTECH
BWa#, BWb#
A
SA0 and SA1 are advancing for the four word burst in the sequence defined by the state of the MODE input.
is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on
this waveform, CE2 is HIGH.
(Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM.
when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
(See Note)
ADDRESS
ADV/LD#
2
; D(A
1
CKE#
) represents the first input to the external address A1. D(A
R/W#
CLK
OE#
CE#
DQ
2
+1) represents the next input data in the burst sequence of the base address A
BW(A
A
1
1
)
t
SD
Write
t
t
t
t
t
t
S
S
S
S
S
S
BW(A
D(A
A
2
1
)
2
t
)
HD
Write
t
t
t
t
t
t
H
H
H
H
H
H
, INC.
BW(A
D(A
2
2
+1)
)
t
KC
WRITE TIMING
t
KL
BW(A
D(A
2
2
256K X 18 FLOW-THROUGH ZBL SRAM
+2)
+1)
11
BW(A
D(A
2
2
+3)
+2)
2
Burst Write
t
KH
) represents the first input to the external address
(CKE# HIGH, eliminates
current L-H clock edge)
Galvantech, Inc. reserves the right to change products or specifications without notice.
D(A
BW(A
2
(Burst Wraps around
+3)
2
)
to initial state)
2
, etc. where address bits
GVT71256ZB18
D(A
2
)
Deselect