gvt71256b18 ETC-unknow, gvt71256b18 Datasheet

gvt71256b18

Manufacturer Part Number

gvt71256b18

Description

256k Synchronous Burst Sram

Manufacturer

ETC-unknow

Datasheet

1.GVT71256B18.pdf (13 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

gvt71256b18T-8

Quantity:

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

gvt71256b18T-8

Quantity:

117

Current page: 1 of 13
Download datasheet (145Kb)

FEATURES

• Fast access times: 7.5, 8, 8.5, and 10ns

• Fast clock speed: 117, 100, 90, and 50 MHz

• Provide high performance 2-1-1-1 access rate

• Fast OE# access times: 4.0ns

• 3.3V -5% and +10% power supply

• 5V tolerant inputs except I/O’s

• Clamp diodes to VSSQ at all inputs and outputs

• Common data inputs and data outputs

• BYTE WRITE ENABLE and GLOBAL WRITE control

• Three chip enables for depth expansion and address

• Address, data and control registers

• Internally self-timed WRITE CYCLE

• Burst control pins (interleaved or linear burst sequence)

• Automatic power-down for portable applications

• High density, high speed packages

OPTIONS

• Timing

• Packages

Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051

Tel (408) 566-0688

Rev. 2/98

GALVANTECH

SYNCHRONOUS

BURST SRAM

FLOW-THROUGH

pipeline

7.5ns access/8.5ns cycle

8ns access/10ns cycle

8.5ns access/11ns cycle

10ns access/20ns cycle

100-pin TQFP

Fax (408) 566-0699

MARKING

-7

-8

-9

-10

, INC.

256K X 18 SYNCHRONOUS BURST SRAM

GENERAL DESCRIPTION

employs high-speed, low power CMOS designs using

advanced

technology. Each memory cell consists of four transistors and

two high valued resistors.

SRAM cells with advanced synchronous peripheral circuitry

and a 2-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE#), depth-expansion chip enables (CE2# and

CE2), burst control inputs (ADSC#, ADSP#, and ADV#),

write enables (WEL#, WEH#, and BWE#), and global write

(GW#).

burst mode control (MODE), and sleep mode control (ZZ).

The data outputs (DQ), enabled by OE#, are also

asynchronous.

address status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance pin

(ADV#).

chip to initiate self-timed WRITE cycle. WRITE cycles can

be one or two bytes wide as controlled by the write control

inputs. Individual byte enables allow individual bytes to be

written. WEL# controls DQ1-DQ8 and DQP1. WEH#

controls DQ9-DQ16 and DQP2. WEL# and WEH# can be

active only with BWE# being LOW. GW# being LOW causes

all bytes to be written.

supply and all outputs operate on a +2.5V supply. All inputs

and outputs are JEDEC standard JESD8-5 compatible. The

device is ideally suited for 486, Pentium

PowerPC

wide synchronous data bus.

The Galvantech Synchronous Burst SRAM family

The GVT71256B18 SRAM integrates 262,144x18

Asynchronous inputs include the output enable (OE#),

Addresses and chip enables are registered with either

Address, data inputs, and write controls are registered on-

The GVT71256B18 operates from a +3.3V core power

256K x 18 SRAM

+3.3V SUPPLY WITH CLOCKED,

REGISTERED INPUTS, BURST COUNTER

systems and for systems that are benefited from a

triple-layer

polysilicon,

GVT71256B18

PowerPC is a trademark of IBM Corporation.

Pentium is a trademark of Intel Corporation.

Galvantech, Inc. reserves the right to change

double-layer

products or specifications without notice.

, 680x0, and

metal

Related parts for gvt71256b18

gvt71256b18 Summary of contents

Page 1

... DQ9-DQ16 and DQP2. WEL# and WEH# can be active only with BWE# being LOW. GW# being LOW causes all bytes to be written. The GVT71256B18 operates from a +3.3V core power supply and all outputs operate on a +2.5V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. The ...

Page 2

... February 10, 1998 Rev. 2/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM UPPER BYTE WRITE D Q LOWER BYTE WRITE D Q ENABLE D Q Input Register Address Register CLR Binary Counter & Logic 2 GVT71256B18 DQ1-DQ16 DQP1 DQP2 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 3

... All synchronous inputs must meet setup and hold times around the clock’s rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP#. Chip Enable: This active LOW input is used to enable the device. 3 GVT71256B18 A10 80 ...

Page 4

... No Connect: These signals are not internally connected. Third Address Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A10 A...A00 A...A01 A...A01 A...A00 Third Address Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 A...A01 A...A10 4 GVT71256B18 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 5

... BWE# WEH# WEL GVT71256B18 ADV# WRITE# OE# CLK L-H High L-H High L-H High L-H High L-H High L L-H High-Z ...

Page 6

... < VCC IL OUT VCC VCCQ SYM TYP or > Icc 150 SB2 SB3 I 40 SB4 ; VCC = MAX GVT71256B18 MIN MAX UNITS NOTES 2.0 VCC+0.3 V 2.0 4.6 V -0.3 0 2.4 V 0.4 V 3.135 3.6 V 3.135 3 -10 UNITS NOTES 370 ...

Page 7

... C I VCC = 3. CONDITIONS SYMBOL TQFP TYP Still air, soldered on 4. 1.125 inch 4-layer PCB JC OUTPUT LOW VOLTAGE m ax VOL (V) -105 -0.5 -105 0 -105 0.4 -83 0.8 -70 1.25 -30 1.6 -10 2.8 0 3.2 0 3.4 7 GVT71256B18 - MIN MAX MIN MAX UNITS 4.5 4.5 ns 4.5 4 3.5 2 3.5 ns 4.0 4 ...

Page 8

... See Figures 1 and 2 15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig / increases with greater t KQHZ is less o C and 20ns cycle time. 8 GVT71256B18 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF Fig. 2 OUTPUT LOAD EQUIVALENT ...

Page 9

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. February 10, 1998 Rev. 2/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM READ TIMING OEQ t OELZ Q(A1) Q(A2) Q(A2+1) 9 GVT71256B18 t H Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ Galvantech, Inc. reserves the right to change products or specifications without notice. Q(A2+2) ...

Page 10

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. February 10, 1998 Rev. 2/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM WRITE TIMING OEHZ D(A1) D(A2) D(A2+2) D(A2+2) BURST WRITE 10 GVT71256B18 D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE Galvantech, Inc. reserves the right to change products or specifications without notice. D(A3+2) ...

Page 11

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. February 10, 1998 Rev. 2/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM READ/WRITE TIMING Q(A2) D(A3) Q(A4) Single Write 11 GVT71256B18 A5 Q(A4+1) Q(A4+2) Q(A4+3) D(A5) D(A5+1) Burst Read Burst Write Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 12

... GALVANTECH 100 Pin TQFP Package Dimensions # 1 1.40 + 0.05 1.60 Max Note: All dimensions in Millimeters February 10, 1998 Rev. 2/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM 16.00 + 0.10 14.00 + 0.10 0.65 Basic 12 GVT71256B18 0.30 + 0.08 0.60 + 0.15 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 13

... Galvantech Prefix Part Number February 10, 1998 Rev. 2/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM 13 GVT71256B18 Speed (7 = 7.5ns access/8.5ns cycle 8 = 8.0ns access/10ns cycle 9 = 8.5ns access/11ns cycle 10 = 10ns access/20ns cycle) Package (T = 100 PIN TQFP) Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Related keywords

gvt71256b18 datasheet
gvt71256b18 data sheet
gvt71256b18 pdf datasheet
gvt71256b18 component
gvt71256b18 part
gvt71256b18 distributor
gvt71256b18 RoHS
gvt71256b18 datasheet download