k7r161882b Samsung Semiconductor, Inc., k7r161882b Datasheet - Page 13

• Manufacturer Part Number: k7r161882b
• Description: 512kx36-bit, 1mx18-bit, 2mx9-bit Qdrtm Ii B2 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7R163682B
K7R160982B
K7R161882B
AC TIMING CHARACTERISTICS
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
Clock
Clock Cycle Time (K, K, C, C)
Clock Phase Jitter (K, K, C, C)
Clock High Time (K, K, C, C)
Clock Low Time (K, K, C, C)
Clock to Clock (K↑ → K↑, C↑ → C↑)
Clock to data clock (K↑ → C↑, K↑→ C↑)
DLL Lock Time (K, C)
K Static to DLL reset
Output Times
C, C High to Output Valid
C, C High to Output Hold
C, C High to Echo Clock Valid
C, C High to Echo Clock Hold
CQ, CQ High to Output Valid
CQ, CQ High to Output Hold
C, High to Output High-Z
C, High to Output Low-Z
Setup Times
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
2. Control signal are R and W.
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
In case of BW
The specs as shown do not imply bus contention because tCHQX
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
PARAMETER
0
,BW
1
(BW
2
, BW
3
, also for x36) signal follow the data setup/hold times.
SYMBOL
t
t
t
t
t
t
t
KC reset
t
CQHQV
CQHQX
t
t
t
t
t
CHCQV
CHCQX
t
t
t
t
t
t
KC lock
CHQX1
t
t
KC var
t
KHKH
KHKH
KHCH
CHQV
CHQX
CHQZ
DVKH
KHDX
KHKL
KLKH
AVKH
KHAX
IVKH
KHIX
(V
512Kx36 & 1Mx18 & 2Mx9 QDR
DD
=1.8V±0.1V, T
1024
-0.45
-0.45
-0.30
-0.45
MIN
4.00
1.60
1.60
1.80
0.00
0.35
0.35
0.35
0.35
0.35
0.35
30
-25
- 13 -
MAX
8.40
0.20
1.80
0.45
0.45
0.30
0.45
1
is a MIN parameter that is worst case at totally different test conditions
1
A
is bigger than tCHQZ.
=0°C to +70°C)
1024
-0.45
-0.45
-0.35
-0.45
MIN
5.00
2.00
2.00
2.20
0.00
0.40
0.40
0.40
0.40
0.40
0.40
30
-20
MAX
8.40
0.20
2.30
0.45
0.45
0.35
0.45
1024
-0.50
-0.50
-0.40
-0.50
MIN
6.00
2.40
2.40
2.70
0.00
0.50
0.50
0.50
0.50
0.50
0.50
30
Rev. 5.0 July 2006
-16
TM
MAX
8.40
0.20
2.80
0.50
0.50
0.40
0.50
II b2 SRAM
UNITS NOTES
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
3
3
7
7
3
3
2