k7n163631b-qc250 Samsung Semiconductor, Inc., k7n163631b-qc250 Datasheet - Page 14

• Manufacturer Part Number: k7n163631b-qc250
• Description: 512kx36 & 1mx18-bit Pipelined Ntram
• Manufacturer: Samsung Semiconductor, Inc.

K7N163631B
K7N161831B
Dout
AC TIMING CHARACTERISTICS
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High (WE, BW
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (WE, BW
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
5. To avoid bus contention, At a given voltage and temperature t
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
(0°C,3.465V) than t
Both cases must meet setup and hold times.
The specs as shown do not imply bus contention because t
Output Load(A)
PARAMETER
Zo=50Ω
HZC
, which is a Max. parameter(worst case at 70°C,3.135V)
X
)
X
)
RL=50Ω
SYMBOL
t
t
t
t
* Including Scope and Jig Capacitance
t
HZOE
t
t
ADVS
t
t
ADVH
t
t
t
t
LZOE
t
t
CYC
t
t
t
t
t
t
t
CEH
t
CSH
LZC
HZC
t
CES
CSS
PDS
PUS
OH
WS
WH
CD
OE
CH
CL
AS
DS
AH
DH
VL=1.5V for 3.3V I/O
V
DDQ
MIN
4.0
1.5
1.5
1.7
1.7
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
512Kx36 & 1Mx18 Pipelined NtRAM
0
2
2
-
-
-
-
LZC
Fig. 1
LZC
- 14 -
/2 for 2.5V I/O
is more than t
is a Min. parameter that is worst case at totally different test conditions
-25
353Ω / 1538Ω
MAX
HZC.
2.6
2.6
2.6
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Dout
Output Load(B),
(for t
LZC
, t
MIN
6.0
1.5
1.5
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
2
2
LZOE
-
-
-
-
, t
Rev. 3.0 April 2006
HZOE
-16
& t
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
HZC
319Ω / 1667Ω
MAX
5pF*
3.5
3.5
3.0
3.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
)
UNIT
cycle
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TM