k6f2008s2e Samsung Semiconductor, Inc., k6f2008s2e Datasheet
k6f2008s2e
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k6f2008s2e Summary of contents
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... K6F2008S2E Family Document Title 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial Draft 1.0 Finalize The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. ...
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... SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. GENERAL DESCRIPTION The K6F2008S2E families are fabricated by SAMSUNG s advanced Full CMOS process technology. The families support various operating temperature ranges and have various pack- age types for user flexibility of system design. The families also supports low data retention voltage for battery back-up opera- tion with low data retention current ...
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... K6F2008S2E Family PRODUCT LIST Part Name K6F2008S2E-YF70 K6F2008S2E-YF85 FUNCTIONAL DESCRIPTION means don t care (Must be high or low states) ABSOLUTE MAXIMUM RATINGS Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss ...
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... K6F2008S2E Family RECOMMENDED DC OPERATING CONDITIONS Item Supply voltage Ground Input high voltage Input low voltage Note: 1. Industrial Product unless otherwise specified Overshoot: Vcc+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. ...
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... K6F2008S2E Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.1V Output load (See right): C =100pF+1TTL L C =30pF+1TTL L AC CHARACTERISTICS (Vcc=2.3~2.7V, Industrial product: T Parameter List Read Cycle Time ...
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... K6F2008S2E Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address High-Z Data out NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6F2008S2E Family TIMING WAVEFORM OF WRITE CYCLE(1) Address Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address Data in Data out (WE Controlled CW( CW(2) t WP(1) t AS( Data Valid t WHZ (CS Controlled CW(2) AS( WP( Data Valid ...
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... K6F2008S2E Family TIMING WAVEFORM OF WRITE CYCLE(3) Address Data in Data out NOTES (WRITE CYCLE write occurs during the overlap of a low CS CS going high and WE going low : A write end at the earliest transition among measured from the begining of write to the end of write. ...
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... K6F2008S2E Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #1 0.50 0.0197 #16 0.25 TYP 0.010 0~8 0.45~0.75 0.018~0.030 13.40 0.20 0.528 0.008 #32 #17 11.80 0.10 +0.10 0.465 0.15 0.004 -0.05 +0.004 0.006 -0.002 0. 0.020 9 CMOS SRAM Units: millimeters(inches) 0. 0.010 1.00 0.10 0.039 0.004 0.05 MIN 0.002 1.20 MAX 0.047 Revision 1.0 September 2001 ...