k7r321882c Samsung Semiconductor, Inc., k7r321882c Datasheet
k7r321882c
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k7r321882c Summary of contents
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... K7R323682C K7R321882C K7R320982C 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ...
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... K7R323682C K7R321882C K7R320982C Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDR Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Put the data in the table of DC Characteristics, Pin Capacitance and Thermal Resistance. 0.2 1. Add 300MHz Bin 2. Change AC Characteristics. 0.3 1. Change Samsung JEDEC Code in ID REGISTER DEFINITION 1.0 1. Final 2. Change Vss/SA to NC/SA in Pin Configuration 1 ...
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... MEMORY ARRAY SELECT OUTPUT CONTROL - SRAM Part Cycle Access Number Time K7R323682C-F(E)C(I)30 3.3 K7R323682C-F(E)C(I)25 4.0 K7R323682C-F(E)C(I)20 5.0 K7R321882C-F(E)C(I)30 3.3 K7R321882C-F(E)C(I)25 4.0 K7R321882C-F(E)C(I)20 5.0 K7R320982C-F(E)C(I)30 3.3 K7R320982C-F(E)C(I)25 4.0 K7R320982C-F(E)C(I)20 5 (or 36) (or 36) 36 (or 18) Q(Data Out) (Echo Clock out) Rev. 1.1 August 2006 Unit Time 0.45 ns 0.45 ns 0.45 ns 0.45 ns ...
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... K7R323682C K7R321882C K7R320982C PIN CONFIGURATIONS (TOP VIEW NC/SA* NC/SA* B Q27 Q18 D18 C D27 Q28 D19 D D28 D20 Q19 E Q29 D29 Q20 F Q30 Q21 D21 G D30 D22 Q22 H Doff V V REF DDQ J D31 Q31 D23 K Q32 D32 Q23 L Q33 Q24 D24 ...
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... K7R323682C K7R321882C K7R320982C PIN CONFIGURATIONS (TOP VIEW) K7R321882C(2Mx18 NC/SA D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H Doff V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 ...
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... K7R323682C K7R321882C K7R320982C PIN CONFIGURATIONS (TOP VIEW) K7R320982C(4Mx9 NC/SA Doff V V REF DDQ TDO TCK SA Notes: 1 ...
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... K and K instead of C and C. When the R is disabled after a read operation, the K7R323682C,K7R321882C and K7R320982C will first complete burst read opera- tion before entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state ...
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... K7R320982C Single Clock Mode K7R323682C,K7R321882C and K7R320982C can be operated with the single clock pair K and K, instead for output clocks. To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high during oper- ation. After power up, this device can’t change to or from single clock mode. System flight time and clock skew could not be compen- sated in this mode ...
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... K7R323682C K7R321882C K7R320982C Detail Specification of Power-Up Sequence in QDRII SRAM QDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. • Power-Up Sequence 1. Apply power and keep Doff at low state (All other inputs may be undefined) - Apply VDD before VDDQ - Apply VDDQ before VREF or the same time with VREF 2 ...
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... K7R323682C K7R321882C K7R320982C TRUTH TABLES SYNCHRONOUS TRUTH TABLE Stopped X X Previous state ↑ ↑ ↑ L Din at K(t) X Notes means “Don′t Care”. 2. The rising edge of clock is symbolized by (↑ Before enter into clock stop status, all pending read and write operations will be completed. ...
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... K7R323682C K7R321882C K7R320982C ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on V Supply Relative to V DDQ Voltage on Input Pin Relative Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... K7R323682C K7R321882C K7R320982C AC ELECTRICAL CHARACTERISTICS PARAMETER Input High Voltage Input Low Voltage Notes: 1. This condition is for AC function test only, not for AC parameter test maintain a valid level, the transition edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, V ...
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... K7R323682C K7R321882C K7R320982C THERMAL RESISTANCE PRMETER Junction to Ambient Junction to Case Junction to Pins Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site x θ thermal impedance PIN CAPACITANCE PRMETER Address Control Input Capacitance ...
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... K7R323682C K7R321882C K7R320982C APPLICATION INRORMATION Vt R Data In Data Out Address MEMORY CONTROLLER Return CLK Vt Source CLK Return CLK Vt Source CLK R=50Ω Vt=V SRAM1 Input CQ SRAM1 Input CQ SRAM4 Input CQ SRAM4 Input CQ 1Mx36 & 2Mx18 & 4Mx9 QDR ZQ R=250Ω SRAM ...
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... K7R323682C K7R321882C K7R320982C TIMING WAVE FORMS OF READ AND NOP READ t KHKH t KLKH K t KHKL IVKH KHIX R Q (Data Out) t KHKH C t KHKL Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0. 2. Outputs are disabled one cycle after a NOP. ...
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... K7R323682C K7R321882C K7R320982C TIMING WAVE FORMS OF READ, WRITE AND NOP READ WRITE D2-1 D2-2 D (Data In) Q (Data Out Note address A1=A2, data Q1-1=D2-1, data Q1-2=D2-2. Write data is forwarded immediately as read results. 2.BWx (NWx) assumed active. 1Mx36 & 2Mx18 & 4Mx9 QDR ...
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... K7R323682C K7R321882C K7R320982C IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control ...
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... K7R323682C K7R321882C K7R320982C SCAN REGISTER DEFINITION Part Instruction Register 1Mx36 3 bits 2Mx18 3 bits 4Mx9 3 bits ID REGISTER DEFINITION Revision Number Part (31:29) 1Mx36 000 2Mx18 000 4Mx9 000 Note: Part Configuration /def=010 for 36Mb, /wx=11 for x36, 10 for x18, 00 for x9. /t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O ...
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... K7R323682C K7R321882C K7R320982C JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL Note: 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7R323682C K7R321882C K7R320982C 165 FBGA PACKAGE DIMENSIONS (Lead & Lead-Free) 15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array Symbol Value Units 15 ± 0 ± 0.1 B 1.3 ± 0.1 C 0.35 ± 0.05 D 1Mx36 & 2Mx18 & 4Mx9 QDR Note Symbol ...