k7a803601m Samsung Semiconductor, Inc., k7a803601m Datasheet - Page 2

• Manufacturer Part Number: k7a803601m
• Description: 256kx36 & 512kx18 Synchronous Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7A803601M
K7A801801M
256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
• Three Chip Enables for simple depth expansion with No Data
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A Package
FAST ACCESS TIMES
LOGIC BLOCK DIAGRAM
ADSC
ADSP
Cycle Time
Clock Access Time
Output Enable Access Time
DQPa ~ DQPd
or 2.5V+0.4V/-0.125V for 2.5V I/O
(x=a,b,c,d or a,b)
WEx
DQa
ear burst.
Contention only for TQFP ; 2cycle Enable, 2cycle Disable.
ADV
LBO
CLK
CS
CS
CS
GW
BW
OE
ZZ
1
2
2
0
PARAMETER
~ DQd
7
or DQa0 ~ DQb7
DQPa,DQPb
Symbol -14 -11
t
CYC
t
t
CD
OE
BURST CONTROL
7.2 8.5
4.0 4.2
4.0 4.2
CONTROL
LOGIC
LOGIC
or A
A
0
0
-10 Unit
4.5
4.5
10
~A
~A
18
17
256Kx36 & 512Kx18 Synchronous SRAM
ns
ns
ns
- 2 -
ADDRESS
REGISTER
A
0
GENERAL DESCRIPTION
The K7A803601M and K7A801801M are 9,437,184-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7A803601M and K7A801801M are fabricated using SAM-
SUNG s high performance CMOS technology and is available
in a 100pin TQFP package. Multiple power and ground pins are
utilized to minimize ground bounce.
~A
1
ADDRESS
COUNTER
BURST
1
high, ADSP is blocked to control signals.
or A
A
2
2
~A
~A
A
0
17
18
~A
1
REGISTER
OUTPUT
BUFFER
256Kx36 , 512Kx18
MEMORY
ARRAY
REGISTER
DATA-IN
May 1999
Rev 3.0