w65c51s ETC-unknow, w65c51s Datasheet
w65c51s
Related parts for w65c51s
w65c51s Summary of contents
Page 1
... Asynchronous Communications Interface Adapter (ACIA) 3/7/2006 W65C51S ...
Page 2
WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made ...
Page 3
... The ACIA is designed for maximum-programmed control from the microprocessor (MPU) to simplify hardware implementation. Three separate registers permit the MPU to easily select the W65C51S operating modes and data checking parameters and determine operational status. The Command Register controls parity, receiver echo mode, transmitter interrupt control, the state of the RTSB line, receiver interrupt control and the state of the DTRB line ...
Page 4
FUNCTIONAL DESCRIPTION A block diagram of the ACIA is presented in Figure 2 followed by a description of each functional element of the . device DATA BUS BUFFERS The Data Bus Buffer interfaces the system data lines to the internal ...
Page 5
STATUS REGISTER The Status Register indicates the state of interrupt conditions and other non-interrupt status lines. The interrupt conditions are the Data Set Ready, Data Carrier Detect, Transmitter Data Register Empty and Receiver Data Register Full as reported in bits ...
Page 6
CONTROL REGISTER The Control Register selects the desired baud rate, frequency source, word length and the number of stop bits SBN RCS WL1 WL0 SBR3 SBR2 Bit 7 Stop Bit Number (SBN ...
Page 7
COMMAND REGISTER The Command Register controls specific modes and functions PMC TIC PME REM PMC1 PMC0 TIC1 TIC0 Bits 7-6 Parity Mode Control (PMC Odd parity transmitted/received 0 1 Even parity ...
Page 8
INTERFACE SIGNALS Figure 4 shows the ACIA interface signals associated with the microprocessor and the modem. Figure 5 ACIA Interface Diagram MICROPROCESSOR INTERFACE Reset (RESB) During System initialization a low on the RESB input causes a hardware reset to occur. ...
Page 9
ACIA/MODEM INTERFACE Crystal Pins (XTLI, XTLO) These pins are normally directly connected to the external crystal (1.8432 MHz) to derive the various baud rates. Alternatively, an externally generated clock can drive the XTLI pin, in which case the XTLO pin ...
Page 10
Continuous Data Receive Similar to the Continuous Data Transmit case, the normal operation of this mode is to assert IRQB when the ACIA has received a full data word. This occurs at about the 9/16 point through the Stop Bit. ...
Page 11
Effect of CTSB on Transmitter CTSB is the Clear-to-Send signal generated by the modem normally low (true state) but may go high in the event of some modem problems. When this occurs, the TxD line goes to the ...
Page 12
Echo Mode Timing In Echo Mode, the TxD line re-transmits the data on the RxD line, delayed by ½ of the bit time, as shown in Figure 10. RxD Stop Start TxD P Stop Start Effect of CTSB on Echo ...
Page 13
Overrun in Echo Mode If Overrun occurs in Echo Mode, the Receiver is affected the same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs, the TxD line Framing Error Framing Error is caused ...
Page 14
Effect of DCDB on Receiver DCDB is a modem output indicating the status of the carrier- frequency-detection circuit of the modem. This line goes high for a loss of carrier. Normally, when this occurs, the modem will stop transmitting data ...
Page 15
Transmit Continuous “BREAK” This mode is selected via the ACIA Command Register and causes the Transmitter to send continuous “BREAK” characters, beginning with the next character transmitted. At least one full “BREAK” character will be transmitted, even if the processor ...
Page 16
STATUS REGISTER OPERATION Because of the special functions of the various status bits, there is a suggested sequence for checking them. When an interrupt occurs, the ACIA should be interrogated as follows: 1. Read Status Register This operation automatically clears ...
Page 17
Table 2 Divisor Selection Control Divisor Selected Register for the Internal Bits Counter Divisor Selected 36,864 24,576 16,769 0 ...
Page 18
DIAGNOSTIC LOOP-BACK OPERATING MODES A simplified block diagram for a system incorporating an ACIA is shown in Figure 18. It may be desirable to include in the system a facility for “loop-back” testing, of which there are two kinds. 1. ...
Page 19
... Frequency tolerance (± Resonance mode d. Equivalent resistance (ohm) e. Drive level (mW) f. Shunt capacitance (pF) g. Oscillation mode EXTERNAL 6 XTLI CLOCK 1MO OPEN XTLO CIRCUIT 7 30pF INTERNAL CLOCK Figure 21 Clock Generation W65C51S Unit Max Figure 22 Transmit Timing with External Clock 500 nS 500 nS 500 1 ...
Page 20
Parameter PHI2 Cycle Time PHI2 Pulse Width Address Set-Up Time Address Hold Time RWB Set-Up Time RWB Hold Time Data Bus Set-Up time Data Bus Hold Time Read Access Time (Valid Data) Read Hold Time Bus Active Time (Invalid Data) ...
Page 21
ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Value Supply Voltage -0.3 to +7. Input Voltage Output Voltage V -0 +0.3V OUT CC Operating Temp Commercial 0 to +70 Industrial ...
Page 22
DC CHARACTERISTICS (V = 5. Parameter Input High Voltage Input Low Voltage Input Leakage Current CS0, CS1B, CTSB, DCDB, DSRB, PHI2, RESB, RS0, RS1, RWB, RxD ...
Page 23
Figure 27 28 Pin Plastic Dip Package Dimensions 23 ...
Page 24
... Handle MOS parts only at conductive workstations. 3. Ground all assembly and repair tools. ORDERING INFORMATION W65C51S6TPG-14 The Western Design Center, Inc. 2166 East Brown Road Mesa, Arizona 85213 USA Fax: 480-835-6442 www.westerndesigncenter.com W65C ...
Page 25
... W65C51S6 Samples Errata Sheet for Lot SA1105A Note: The internal feedback resistor was removed from the W65C51S6 and therefore an external feedback resistor is required between XTLI (aka XTAL1) and XTLO (XTAL2). This document will describe the current known errors with the W65C51 ACIA Engineering Samples found by WDC ...
Page 26
... W65C51S6 Samples Errata Sheet for Lot SA0519A Note: The internal feedback resistor was removed from the W65C51S6 and therefore an external feedback resistor is required between XTLI (aka XTAL1) and XTLO (XTAL2). This document will describe the current known errors with the W65C51 ACIA Engineering Samples found by WDC ...