w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 11

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

COMMAND REGISTER BIT DESCRIPTION
Data Terminal Ready (Bit 0)
This bit enables all selected interrupts and controls the state of the Data Terminal Ready (DTRB) line. A
0 indicates the microcomputer system is not ready by setting the DTRB line high. A 1 indicates the
microcomputer system is ready by setting the DTRB line low.
Receiver Interrupt Control (Bit 1)
This bit disables the Receiver from generating an interrupt when set to a 1. The Receiver interrupt is
enabled when this bit is set to a 0 and Bit 0 is set to a 1.
Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTSB) line and the Transmitter interrupt.
Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 enables the Receiver Echo Mode. When bit 4 is a 1 bits 2
and 3 must be 0. In the Receiver Echo Mode, the Transmitter returns each transmission received by the
Receiver delayed by one-half bit time.
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0 disables parity bit generation by the Transmitter
and parity bit checking by the Receiver. A 1 bit enables generation and checking of parity bits.
Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the Transmitter (W65C51N device currently will only
generate a MARK parity bit) and the type of parity check done by the Receiver (even, odd or no check).
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