k4x56163pi Samsung Semiconductor, Inc., k4x56163pi Datasheet - Page 11

• Manufacturer Part Number: k4x56163pi
• Description: 16mx16 Mobile Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4X56163PI - L(F)E/G
12. DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
NOTE :
1) It has +/- 5°C tolerance.
2) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
3) IDD specifications are tested after the device is properly intialized.
4) Input slew rate is 1V/ns.
5) Definitions for IDD: LOW is defined as V
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Deep Power Down Current
Please contact Samsung for more information.
Parameter
HIGH is defined as V
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
Symbol
IDD2PS
IDD2NS
IDD3PS
IDD3NS
IDD4W
IDD2N
IDD3N
IDD4R
IDD2P
IDD3P
IDD0
IDD5
IDD6
IDD8
tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid com-
mands; address inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts;
I
address inputs are SWITCHING; 50% data change each burst transfer
one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
CKE is LOW; t CK = t CKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Deep Power Down Mode Current
IN
OUT
IN
≥ 0.9 * VDDQ ;
≤ 0.1 * VDDQ ;
=0 mA;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
SS
= 0V, Tc = -25 to 85°C)
Test Condition
- 14 -
- E
- G
Parameter
Full Array
Full Array
1/2 Array
1/4 Array
1/2 Array
1/4 Array
Mobile DDR SDRAM
DDR333 DDR266 Unit Note
45
110
100
200
160
140
150
135
130
50
15
25
20
90
8
1)
0.3
0.3
10
5
2
450
300
250
300
250
225
45
12
25
20
95
75
85
85
8
October 2007
mA
mA
mA
mA
mA
mA
mA
uA
uA
°C
2