M25P10-AVMB3/X NUMONYX [Numonyx B.V], M25P10-AVMB3/X Datasheet
M25P10-AVMB3/X
Related parts for M25P10-AVMB3/X
M25P10-AVMB3/X Summary of contents
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... JEDEC standard two-byte signature (2011h) – RES instruction, one-byte signature (10h), for backward compatibility ■ More than 20 years’ data retention ■ Packages – ECOPACK® (RoHS compliant) December 2007 SO8 (MN) 150 mil width VFQFPN8 (MP) (MLP8) UFDFPN8 (MB Rev 11 M25P10-A 1/51 www.numonyx.com 1 ...
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... Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 11 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Write Status Register (WRSR 2/51 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 M25P10-A ...
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... M25P10-A 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down and Read Electronic Signature (RES Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... Table 22. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 23. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead package mechanical data47 Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4/51 M25P10-A ...
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... M25P10-A List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO, VFQFPN and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9 ...
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... Description 1 Description The M25P10 Mbit (128 Kbit x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide ...
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... M25P10-A Figure 2. SO, VFQFPN and UFDFPN8 connections 1. There is an exposed die paddle on the underside of the MLP8 packages. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical M25P10 ...
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... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). 8/51 M25P10-A ...
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... Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P10-A is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...
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... R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA 10/ µs <=> the application must ensure that the Bus p MSB M25P10-A MSB AI01438B ...
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... M25P10-A 4 Operating features 4.1 Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P10-A features the following data protection mechanisms: ● Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...
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... M25P10-A Table 2. Protected area sizes Status Register content BP1 BP0 bit bit 0 0 none 0 1 Upper quarter (sector Upper half (two sectors: 2 and All sectors (four sectors and 3) none 1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) bits are ...
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... Operating features Figure 5. Hold condition activation C HOLD 14/51 Hold condition (standard use) M25P10-A Hold condition (non-standard use) AI02029D ...
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... M25P10-A 5 Memory organization The memory is organized as: ● 131,072 bytes (8 bits each) ● 4 sectors (256 Kbits, 32768 bytes each) ● 512 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is sector or bulk erasable (bits are erased from but not page erasable. ...
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... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. 16/51 Table 4. M25P10-A ...
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... M25P10-A Table 4. Instruction set Instruction WREN Write Enable WRDI Write Disable (1) RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase BE Bulk Erase DP Deep Power-down Release from Deep Power- ...
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... Write Status Register (WRSR) instruction completion ● Page Program (PP) instruction completion ● Sector Erase (SE) instruction completion ● Bulk Erase (BE) instruction completion Figure 8. Write Disable (WRDI) instruction sequence 18/51 (Figure 8) resets the Write Enable Latch (WEL) bit Instruction D High Impedance Q M25P10 AI03750D ...
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... M25P10-A 6.3 Read Identification (RDID) The Read Identification (RDID) instruction is available in products with process technology code X and Y. The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (11h) ...
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... Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W) is driven Low). In this mode, the 20/ Figure 10. BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit Table 2) becomes protected M25P10-A b0 WIP ...
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... M25P10-A non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance ...
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... As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. 22/51 Figure 11. Table 2. The Write Status Register (WRSR) instruction also allows the M25P10 Table 7. ...
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... M25P10-A Regardless of the order of the two events, the Hardware Protected mode (HPM) can be entered: ● by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low ● driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit ...
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... High Impedance Q 1. Address bits A23 to A17 are Don’t care. 24/51 Figure 12 Instruction 24-bit address MSB Data Out MSB M25P10-A Data Out 2 7 AI03748D ...
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... M25P10-A 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
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... Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP1, BP0) bits (see 26/51 Figure 14. 6)). Table 3 and Table 2) is not executed. M25P10-A Table 16: Instruction ...
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... M25P10-A Figure 14. Page Program (PP) instruction sequence MSB 1. Address bits A23 to A17 are Don’t care Instruction 24-bit address MSB Data byte 2 Data byte 3 ...
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... D 1. Address bits A23 to A17 are Don’t care. 28/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 15. Table 3 and Table 2) is not executed Instruction MSB 24-bit address AI03751D M25P10 ...
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... M25P10-A 6.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Deep Power-down (DP) instruction sequence 30/51 Figure 17 Instruction M25P10 specified CC1 CC2 before the supply current is reduced Standby mode Deep Power-down mode AI03753D ...
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... Deep Power-down mode. The instruction can also be used to read, on Serial Data output (Q), the 8-bit electronic signature, whose value for the M25P10-A is 10h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the 8-bit electronic signature of the device, and can be applied even if the Deep Power-down mode has not been entered ...
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... Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit electronic signature, for the M25P10-A, is 10h. Figure 19. Release from Deep Power-down (RES) instruction sequence High Impedance Q 32/ ...
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... M25P10-A 7 Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V ● V (min) at power-up, and then for a further delay ● power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included ...
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... Write Inhibit voltage (device grade These parameters are characterized only. 34/51 Program, Erase and Write commands are rejected by the device Chip selection not allowed tVSL tPUW threshold WI Parameter (min low M25P10-A Read access allowed Device fully accessible time AI04009C Min Max ...
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... M25P10-A 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device above the rating listed in cause permanent damage to the device ...
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... Output timing reference voltages 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 21. AC measurement I/O waveform 36/51 Parameter Condition Device grade 6 Device grade °C Parameter Input levels timing reference levels 0.8V CC 0.2V CC M25P10-A Min Max (1) 2.3 3.6 –40 85 –40 125 Min Max Unit 100,000 ...
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... M25P10-A Table 13. Capacitance Symbol C Output capacitance (Q) OUT C Input capacitance (other pins Sampled only, not 100% tested Table 14. DC characteristics (device grade 6) Symbol I Input Leakage current LI I Output Leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) ...
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... MHz 0.9 MHz –0 –100 μA V –0.2 CC Table 10 and Table 12 Min Typ 5 1.4 0.4+ (2) n*1/256 0.65 1.7 M25P10-A (2) Max Unit ± 2 µA ± 2 µA 100 µA 50 µ ...
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... M25P10-A Table 17. Instruction times (device grade 3) Symbol Alt ( Only for products with process technology code °C. 3. Preliminary data. 4. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤ ...
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... S High to Standby mode with Read Electronic Signature . C Table 10 and Table 12 Min Typ Max D. 0.1 0 100 100 1 M25P10-A Unit MHz MHz ns ns V/ns V/ µs (5) µs (5) µs ...
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... M25P10-A Table 19. AC characteristics (40 MHz operation, device grade 6) 40 MHz available for products marked since week 20 of 2004, only Symbol Alt ( CLH ( CLL (3) t CLCH (3) t CHCL t t SLCH CSS t CHSL t t DVCH DSU ...
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... S High to Standby mode without Read Electronic Signature S High to Standby mode with Read Electronic Signature . C (1)(2) Table 10 and Table 12 Min Typ D.C. D. 0.1 0 100 100 M25P10-A Max Unit 50 MHz 25 MHz ns ns V/ns V/ μ ...
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... M25P10-A Figure 22. Serial input timing S tCHSL Figure 23. Write Protect Setup and Hold timing during WRSR when SRWD=1 W tWHSL tSLCH tDVCH tCHDX MSB IN High Impedance High Impedance DC and AC parameters tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN AI01447C tSHWL AI07439 43/51 ...
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... DC and AC parameters Figure 24. Hold timing HOLD Figure 25. Output timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN 44/51 tHLCH tCHHL tCHHH tHLQZ tCH tCLQV tQLQH tQHQL M25P10-A tHHCH tHHQX AI02032 tCL tSHQZ LSB OUT AI01449e ...
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... M25P10-A 11 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 26. SO8 narrow – ...
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... θ millimeter Typ Min Max 0.85 1.00 0.00 0.05 0.65 0.20 0.40 0.35 0.48 6.00 5.75 3.40 3.20 3.60 5.00 4.75 4.00 3.80 4.20 1.27 0.60 0.50 0.75 12° M25P10 VFQFPN-01 inches Typ Min Max 0.033 0.039 0.000 0.002 0.026 0.008 0.016 0.014 0.019 0.236 0.226 0.134 0.126 0.142 0.197 0.187 0.157 0.150 0.165 0.050 0.024 0.020 0.029 12° ...
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... M25P10-A Figure 28. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead package outline 1. Drawing is not to scale. Table 23. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead package mechanical data Symbol ...
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... For more information on how to identify products by the process identification letter, please refer to AN1995: Serial Flash memory device marking. 4. Only available for grade 6 devices. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 48/51 M25P10-A (2) ( M25P10 ...
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... M25P10-A 13 Revision history Table 25. Document revision history Date Revision 25-Feb-2001 12-Sep-2002 13-Dec-2002 21-Feb-2003 24-Nov-2003 08-Mar-2005 01-Apr-2005 01-Aug-2005 14-Apr-2006 1.0 Document written. VFQFPN8 package (MLP8) added. Clarification of descriptions of 1.1 entering Standby Power mode from Deep Power-down mode, and of terminating an instruction sequence or data-out sequence. Typical Page Program time improved. Write Protect setup and hold times specified, for applications that switch Write Protect to exit the Hardware 1 ...
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... Code of the UFDFPN8 package modified. 10 Small text changes. 11 Applied Numonyx branding. Changes Table 18 and Table 19. Figure 26 in Table 9: Absolute IO and modified Figure 3: Bus master and bus. changed. added. in Table 14 and f in Table 20. CC3 R conditions, Table 15: DC 3), and Table 17: Instruction times (device scheme. M25P10-A and ...
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... M25P10-A INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...