CT2566-FP AEROFLEX [Aeroflex Circuit Technology], CT2566-FP Datasheet - Page 3

• Manufacturer Part Number: CT2566-FP
• Description: CT2566 MIL-STD-1553 to Microprocessor Interface Unit
• Manufacturer: AEROFLEX [Aeroflex Circuit Technology]

Aeroflex Circuit Technology
PIN NO.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
4
5
6
7
8
9
SELECT
RD/WR
READYD
EXTEN
TAGEN
EOM
SOM
STATERR
ADRINC
MEM/REG
CLOCK IN
LOOPERR
BUSREQ
BUSGRNT
Not Used
MEMCS
OE
N/C
NBGRNT
+ 5 Volt
D15
D13
D11
D09
D07
D05
D03
NAME
Table 2 – Pin Functions (78 Pin DIP)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
Select. When active, selects CT2566 for operation.
Read/Write. Controls CPU bus data direction.
Ready Data. When active indicates data has been received
from, or is available to the CPU.
External Enable. Output from CT2566 to enable output from
external devices. Same timing as MEMOE.
Tag Enable. Enables an external time tag counter for
transferring the time tag word into memory.
End of Message. Input from 1553 device indicating end of
message.
Start of Message. Input from 1553 device indicating start of
message in RTU mode.
Status Error. Input from 1553 device when status word has
either a bit set or unexpected RT address (in BC mode only).
Address Increment. Sent from 1553 device to increment
address counter following word transfer.
Memory/Register. Input from CPU to select memory or
register data transfer.
Clock input; 50% duty cycle, 12MHz, max.
Loop Error. Input from 1553 device if short loop BIT fails.
Bus Request. When active, indicates 1553 device requires
use of the address/data bus.
Bus Grant. Handshake output to 1553 device in response to
BUS REQUEST indicating address/data bus available to
1553 device.
-
Memory Chip Select. Low from CT2566 to enable external
RAM. Used with 4K x 4 RAM type device to read RAM or
used in conjunction with MEMWR to write data into RAM.
Output Enable. Input from 1553 device used to enable
memory on the parallel bus.
Not Used.
Low pulse from 1553 device preceding start of received new
protocol sequence. Used with superseding command to reset
DMA in progress.
Logic power supply.
Data Bus Bit 15 (MSB).
Data Bus Bit 13.
Data Bus Bit 11.
Data Bus Bit 9.
Data Bus Bit 7.
Data Bus Bit 5.
Data Bus Bit 3.
3
DESCRIPTION
SCDCT2566 REV B 8/10/99 Plainview NY [phone]