IDT2305-1 IDT [Integrated Device Technology], IDT2305-1 Datasheet
IDT2305-1
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IDT2305-1 Summary of contents
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... Distributes one clock input to one bank of five outputs • Zero Input-Output Delay • Output Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT2305-1 for Standard Drive • IDT2305-1H for High Drive • No external RC network required • Operates at 3. • Power down mode • ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER PIN CONFIGURATION 1 REF CLK2 2 3 CLK1 GND 4 SOIC TOP VIEW APPLICATIONS: • SDRAM • Telecom • Datacom • PC Motherboards/Workstations • Critical Path Delay Designs PIN DESCRIPTION Pin Name Pin Number REF (1) 1 CLK2 (2) 2 CLK1 (2) 3 GND ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER OPERATING CONDITIONS - COMMERCIAL Symbol Parameter V Supply Voltage DD T Operating Temperature (Ambient Temperature Load Capacitance < 100MHz L Load Capacitance 100MHz - 133MHz C Input Capacitance IN DC ELECTRICAL CHARACTERISTICS - COMMERCIAL Symbol Parameter V Input LOW Voltage Level IL V Input HIGH Voltage Level ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER SWITCHING CHARACTERISTICS (2305-1H) - COMMERCIAL Symbol Parameter t Output Frequency 1 ÷ t Duty Cycle = ÷ t Duty Cycle = Rise Time 3 t Fall Time 4 t Output to Output Skew 5 t Delay, REF Rising Edge to CLKOUT Rising Edge 6 t Device-to-Device Skew ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER SWITCHING CHARACTERISTICS (2305-1) - INDUSTRIAL Symbol Parameter t Output Frequency 1 ÷ t Duty Cycle = Rise Time 3 t Fall Time 4 t Output to Output Skew 5 t Delay, REF Rising Edge to CLKOUT Rising Edge 6 t Device-to-Device Skew 7 t Cycle-to-Cycle Jitter ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER ZERO DELAY AND SKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER SWITCHING WAVEFORMS t1 t2 1.4V 1.4V Duty Cycle Timing 2V 0.8V 0.8V 2V Output t3 All Outputs Rise/Fall Time TEST CIRCUITS V DD μ 0.1 F OUTPUTS V DD μ 0.1 F GND GND Test Circuit 1 (all Parameters Except t8) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Output 1.4V Output 3.3V REF 0V t4 Output ...
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... Number of Loaded Outputs NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V data is calculated from nCVf, where CORE V = Supply Voltage (V Frequency (Hz)) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AND I TRENDS FOR IDT2305-1 (1) ( 33M 66M H z 100M Hz 48 ...
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... Duty Cycle is taken from typical chip measured at 1.4V data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current Number of outputs Capacitance load per output (F Supply Voltage (V Frequency (Hz)) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AND I TRENDS FOR IDT2305-1H (1) ( ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER PACKAGE OUTLINE AND PACKAGE DIMENSIONS - SOIC N INDEX AREA 150 mil (Narrow Body) SOIC In Millimeters COMMON DIMENSIONS SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D SEE VARIATIONS E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 N SEE VARIATIONS α 0° 8° NOTE: 1. For reference only. Controlling dimensions are in mm. ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER ORDERING INFORMATION IDT XXXXX XX Package Device Type Ordering Code IDT2305-1DC IDT2305-1DCG IDT2305-1DCI IDT2305-1DCGI IDT2305-1HDC IDT2305-1HDCI CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X Process Blank I DC DCG 2305-1 2305-1H Package Type 8-Pin SOIC 8-Pin SOIC ...