IDT2309A-1PGG IDT [Integrated Device Technology], IDT2309A-1PGG Datasheet
![no-image](/images/no-image-200.jpg)
IDT2309A-1PGG
Related parts for IDT2309A-1PGG
IDT2309A-1PGG Summary of contents
Page 1
... REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2309A enters power down. In this mode, the device will draw less than 12µA for Commercial Temperature range and less than 25µA for Industrial temperature range, and the outputs are tri-stated ...
Page 2
... IDT2309A 3.3V ZERO DELAY CLOCK BUFFER PIN CONFIGURATION REF 1 2 CLKA1 CLKA2 GND 6 CLKB1 CLKB2 SOIC/ TSSOP TOP VIEW APPLICATIONS: • SDRAM • Telecom • Datacom • PC Motherboards/Workstations • Critical Path Delay Designs PIN DESCRIPTION Pin Name Pin Number ...
Page 3
... Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured (2) DD Measured PLL bypass mode (IDT2309A only) (2) DD Measured the CLKOUT pins of devices DD Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin ...
Page 4
... Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured Measured PLL bypass mode (IDT2309A only) DD Measured the CLKOUT pins of devices DD Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin ...
Page 5
... Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured Measured PLL bypass mode (IDT2309A only) DD Measured the CLKOUT pins of devices DD Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin ...
Page 6
... IDT2309A 3.3V ZERO DELAY CLOCK BUFFER ZERO DELAY AND SKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay ...
Page 7
... IDT2309A 3.3V ZERO DELAY CLOCK BUFFER TEST CIRCUITS V DD 0.1µF OUTPUTS V DD 0.1µF GND GND Test Circuit 1 (all Parameters Except t8) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES CLK OUT 0.1µF C LOAD 0.1µF Test Circuit 2 (t8, Output Slew Rate On -1H Devices 1KΩ OUTPUTS 1KΩ ...
Page 8
... IDT2309A 3.3V ZERO DELAY CLOCK BUFFER ORDERING INFORMATION IDT XXXXX XX Package Process Device Type Ordering Code IDT2309A-1DC IDT2309A-1DCG IDT2309A-1DCGI IDT2309A-1DCI IDT2309A-1HDC IDT2309A-1HDCI IDT2309A-1HPGG IDT2309A-1HPGGI CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES X Blank I DC DCG PG PGG 2309A-1 ...